Cortex-M3 core commands

1. _ DSB () command:

Data Synchronization barrier, this function acts as a special kind of data memory barrier. It completes when all explicit memory accesses before this instruction complete.

Instance (the clock source frequency of timer is lower than the MCU clock speed ):

Void timer0_irqhandler (void)
{
/* Clear interrupt source */
Timer-> IFC = timer_ifc_of;
/* Flushing instructions to make sure that the interrupt is not re-triggered */
/* This may be required when the peripheral clock is slower than the core */
_ DSB (); // wait until the ram access is completed to prevent repeated interruptions.

/* Stopping timer */
Timer-> cmd = timer_assist_stop;

}