Design practice of more complex sequential logic circuits

1. Function diagram

The M0 sends data to M1,M1 to access the data and assigns it to the serial SDA, which is passed to M0.

2. Timing Diagram

As can be seen from the timing diagram: The point is, this sentence is the most important, understand ha, if scl=1, then SDA from the high-low-time serial data flow start; if scl=1, then SDA from low to high time serial data flow end, if scl=0, then our SDA data can change.

3. State diagram

This is the description of the time series state diagram, we can see that the state diagram is just the state, which is the state of the timing, pay attention to the behavior of CLK. From the condition of the state transition, the key to the success of the conversion is to understand the timing diagram, that is: What conditions are the start, what conditions represent the data??

4. M1 procedure

1 //M1 Program2 module PTOSDA (rst,sclk,ack,scl,sda,data);3 4Input Sclk,rst;//external clock and reset5input[3:0] data;//External Data6Output ack;//Request7Output SCL;//M1 's Clock8Output SDA;//M1 Data Cable9 TenReg SCL,LINK_SDA,ACK,SDABUF;//bus switching, data serial storage variables Onereg[3:0]databuf;//M1 Internal data storage Areg[7:0]state;//State Variables -  - //Nine kinds of states, how to think???  theParameter ready=8'b0000_0000,//Wait -start=8'b0000_0001,//Start -bit1=8'b0000_0010,//Data 1 -Bit2=8'b0000_0100,//Data 2 +bit3=8'b0000_1000,//Data 3 -bit4=8'b0001_0000,//Data 4 +bit5=8'b0010_0000,//Data 5 Astop=8'b0100_0000,//End atidle=8'b1000_0000;//Idle -  -[Email protected] (Posedge sclk or Negedge rst)//set the clock first, that's how it's set up. - begin -         if(!rst) -scl<=1;//M1 's SCL clock needs to be first high in         Else -scl<=~scl;//the data here is twice times the period of the SCLK, passing the SCLK clock signal to the SCL, a method, 5rf you know. to End +      -[Email protected] (Posedge ack)//and accept the data. thedatabuf<=data;//as soon as the request arrives, the data will be passed to Databuf. *      $ //------Master State machine: Generates a control signal, according to the data stored in the DATABUF, the SDA serial signal according to the ProtocolPanax Notoginseng[Email protected] (Negedge sclk or Negedge rst)//this is SCLK. No SCL is triggered with low level -     if(!rst) the begin +link_sda<=0;//disconnecting the bus Astate<=ready;//go to the Ready state thesdabuf<=1;//M1 Transmit data bus open +ack<=0;//Request 0 - End $     Else $ begin -              Case(state) - Ready : the                     if(ACK)// - beginWuyilink_sda<=1;//SDA bus turned on thestate<=start;//go to another start stage - End Wu                     Else     - begin Aboutlink_sda<=0;//SDA bus off $state<=Ready ; -ack<=1;//Request Data - End - Start: A                     if(Scl&&ack)//SCL is high-level, low-level data transfer + begin thesdabuf<=0;//sdabuf Deposit 0 -state<=bit1;//Enter bit1 State $ End the                     Else thestate<=start;//wait for SCL high to arrive the bit1: the                     if(!SCL) - begin insdabuf<=databuf[3];//sdabuf Storage of high -level data thestate<=bit2;//Enter Bit2 State theack<=0;//Close Request About End the                     Else thestate<=bit1;//wait for the SCL to become low, which appears to be the Bit2: +                     if(!SCL) - begin thesdabuf<=databuf[2];Bayistate<=bit3; the End the                     Else -state<=Bit2; - bit3: the                     if(!SCL) the begin thesdabuf<=databuf[1]; thestate<=BIT4; - End the                     Else thestate<=bit3; the BIT4:94                     if(!SCL) the begin thesdabuf<=databuf[0]; thestate<=bit5;98 End About                     Else -state<=BIT4;101                 102 bit5:103                     if(!SCL)104 begin thesdabuf<=0;106state<=stop;107 End108                     Else109state<=bit5; the Stop:111                     if(SCL) the begin113sdabuf<=1; thestate<=Idle; the End the                     Else117state<=stop;118 Idle:119 begin -link_sda<=0;121state<=Ready ;122 End123                 default:124 begin thelink_sda<=0;126state<=1;127state<=Ready ; - End129 Endcase the         131 End the         133Endmodule

Design practice of more complex sequential logic circuits