DM642 Image Storage FAQ

Please help the younger brother, there are some of the following procedures:
1 evmdm642_vdisparamschan.segid = externalheap;
The Fvid module in the Gio class driver specifies the bucket ID that will be used to allocate the video frame buffer to Externalheap
The externalheap is the heap in the external memory, the address is 0x80000000, but the specific Y,CR,CB buffer address is determined by the Mem module allocation in Dsp/bios. There are no definitions in. Map, and in the cmd file. Not in the program either.

I see the information that iom_packet this structure has the destination address of the EDMA transmission, the size and address of the image buffer should be described in the program, the size should be in the evmdm642_vdisparamschan,evmdm642_ Vcapparamschan definition, but I do not see in the program to give Iom_packet address Fu value. I do not know whether to use Iom_packet to define the destination address and size of the EDMA transmission. The source address is a FIFO address

2 One of the Dischan or Capchan channel configurations is: Alignment:buffer byte alignment
Here is the 128-byte alignment, that is, the start address of buffer is a multiple of 128, what this means.

1., but the specific Y,CR,CB buffer address how to determine. Fvid_frame *capframebuf; Fvid_alloc (CAPCHANCH1, &capframebuf); Where CAPCHANCH1 is the fvid handle. Capframebuf->frame.ifrm.y1 is the address of the Y store. CAPFRAMEBUF->FRAME.IFRM.CB1/CR1 is the address of CB CR, these member definitions can be in Fvid. Found in H. But this address and the "VP Port Buffer Address" is two different, the VP port data exceeds the FIFO domain value after triggering EDMA data transfer to the above specified storage area. "But I didn't see the Iom_packet address in the program. I do not know whether to use Iom_packet to define the destination address and size of the EDMA transmission. ” This is in capChanCh1 = Fvid_create (... ) and Fvid_control (... ) is completed in the. 2 This is to increase the cache hit rate, because the l2d row size is 128 bytes, a row of data in the application is often to be continuously obtained, if 128 is aligned, the first pixel of the line miss cause a row to be read into the l2d, the following 127 will hit. That's probably what this means, and this is also recommended in the cache's documentation. If the answer is inaccurate, I hope you will discuss it together.

First of all thank you for your answer, but still some do not understand, again to ask Hehe
For the first problem, the Y,CR,CB buffer specific address is determined.
Fvid_frame *capframebuf;
Fvid_alloc (CAPCHANCH1, &capframebuf); Where CAPCHANCH1 is the fvid handle.
Capframebuf->frame.ifrm.y1 is the address of the Y store.
CAPFRAMEBUF->FRAME.IFRM.CB1/CR1 is the address of CB CR, these member definitions can be in Fvid. Found in H.
This is true, but fvid.h is defined in the image format, there is a consortium, defined such as interlaced (IFRAME) or progressive (pframe) Form, etc., should not be defined CAPFRAMEBUF address it, Capframebuf is a pointer to the structure of a certain image format, the structure of which is composed of y,c and other composition of a format image, Capframebuf->frame.ifram.y1 is the brightness value of interlaced scanning.

Capchan = Fvid_create ("/vp0capture/a/0", Iom_input, &status, (PTR) &evmdm642_vcapparamschan, NULL);
Fvid_control (Dischan, Vport_cmd_edc_base + edc_config, (PTR) &evmdm642_vdisparamssaa7105);
Fvid_control (Capchan, Vport_cmd_edc_base + edc_config, (PTR) &evmdm642_vcapparamssaa7115);
Fvid_control (Dischan, Vport_cmd_start, NULL);
Fvid_control (Capchan, Vport_cmd_start, NULL);
How to see the destination address and size of the Iom_packet EDMA transmission from Fvid_creat and Fvid_control. The specific address of the Y,CR,CB buffer is determined. "
The specific address is indeterminate and is dynamically allocated.
Hopefully you'll find this code (in the vportdis.c of DDK's SRC Video folder).
Static Int _configedma (Ptr chanp, Vportdis_params *params)
{ 。。。。 Slightly
for (i = 0; i < chan->numfrms; i + +) {
if (curaddr = Mem_alloc (Params->segid,chan->bufsz,
params->alignment)) = = Mem_illegal) {
for (j = 0; J < i; J + +) {
Mem_free (Params->segid, Chan->viops[j].frame.ifrm.y1,
CHAN-&GT;BUFSZ);
}
/* Memory allocation fails */
return iom_ealloc;
}
。。。。
for (i = 0; i < Edmachans; i + +) {
Int optFld1 = EDMA_OPT_RMK (
Params->edmapri,
Edma_opt_esize_32bit,
Edma_opt_2ds_yes,
Edma_opt_sum_inc,
Edma_opt_2dd_no,
Edma_opt_dum_none,
Edma_opt_tcint_no,
Edma_opt_tcc_of (0),
Edma_opt_tccm_of (0),
Edma_opt_atcint_no,
Edma_opt_atcc_default,
Edma_opt_pdts_disable,
Edma_opt_pdtd_disable,
Edma_opt_link_yes,
Edma_opt_fs_no
);
Int optfld2a = EDMA_OPT_RMK (

Params->edmapri,
Edma_opt_esize_32bit,
Edma_opt_2ds_yes,
Edma_opt_sum_inc,
Edma_opt_2dd_no,
Edma_opt_dum_none,
(i = = 0?) EDMA_OPT_TCINT_YES:EDMA_OPT_TCINT_NO),
edma_opt_tcc_of (i = = 0 Chan->tcc[0] & 0x0f:0),
edma_opt_tccm_of (i = = 0? chan->tcc[0] >> 4:0),
Edma_opt_atcint_no,
Edma_opt_atcc_default,
Edma_opt_pdts_disable,
Edma_opt_pdtd_disable,
Edma_opt_link_yes,
Edma_opt_fs_no
);
Int optfld2b = EDMA_OPT_RMK (

Params->edmapri,
Edma_opt_esize_32bit,
Edma_opt_2ds_yes,
Edma_opt_sum_inc,
Edma_opt_2dd_no,
Edma_opt_dum_none,
(i = = 0?) EDMA_OPT_TCINT_YES:EDMA_OPT_TCINT_NO),
edma_opt_tcc_of (i = = 0 Chan->tcc[1] & 0x0f:0),
edma_opt_tccm_of (i = = 0? chan->tcc[1] >> 4:0),
Edma_opt_atcint_no,
Edma_opt_atcc_default,
Edma_opt_pdts_disable,
Edma_opt_pdtd_disable,
Edma_opt_link_yes,
Edma_opt_fs_no
);
。。。。。。。。。。
}

Everything you are interested in is in the DDK video driver code.

Thank you so much, I'll look at the code tomorrow. But I see some other examples of video capture, their buffer address is determined, for example, a collection program has the following paragraph: Uint32 capybuffer = 0x80000000; Uint32 capcbbuffer = 0x800675c0; Uint32 capcrbuffer = 0x8009b0a0; Uint32 disybuffer = 0x80100000; Uint32 discbbuffer = 0x801675c0; Uint32 discrbuffer = 0x8019b0a0; There is a general difference between the two. Generally we are directly dealing with the luminance signal, for the kind of random distribution is not with the capframebuf->frame.ifrm.y1, such as a CIF format, (forget), the luminance signal of the matrix how to take out. In addition, if I want to use the ping-pong buffer structure, the two pairs of ping-pong buffer are generally assigned to the SDRAM. The buffer address is either randomly allocated or there is a different allocation method.

"The two are generally different." "There is no real difference between the two, you can specify the destination address of the EDMA (capture) of course." Just fvid this way is more flexible, the ability to transplant, because there is no absolute address in the code. "Generally we are directly dealing with the luminance signal, for the kind of random allocation is not to use capframebuf->frame.ifrm.y1 on the line" Yes, after the image is generally PAL or NTSC format, to write their own CIF conversion code, There is also a way to use the VP port to bring the horizontal sampling, read the field data to achieve vertical sampling (this I did not implement, need to configure the VP port parameters). Two pairs of ping-pong buffer are generally assigned to the SDRAM.  The buffer address is either randomly allocated or there is a different allocation method. I used to put ping-pong into the on-chip ram, so I don't have to consider the consistency issue, as for the use of mem_alloc allocation or self-declared array to see personal interests.

Thank you
Look at the VPORTDIS.C that program, the general know that the Y,CR,CB buffer is randomly assigned in the SEGLD, so that the words are not view-image This command to view the image pull.
In addition, when the FIFO reaches the threshold, a hardware interrupt is triggered, and a EDMA channel is enabled in the Interrupt service program to read the data from the FIFO. How to set up a EDMA interrupt if you want to set up a frame after acquisition. , you need to set the BIOS. The following paragraph I see on the page some unclear white

EDMA Interrupt Settings: Add Edma_intdispatcher () to the Interrupt service table (IST) as EDMA Interrupt Service pickup (ISTP) and use Edma_ Inthook () establishes a connection to the Interrupt service program for the transfer end code of the two brightness edma.
Set 64 EDMA channels to share an interrupt number, when an interrupt occurs, Edma_intdispatcher () first detects the bits in the Cier and CIPR registers, and then calls the interrupt service program that is connected by the Edma_inthook (). After an interrupt occurs, the EDMA channel is triggered by the transfer end code to differentiate which is the current interrupt.
Do not understand is mainly about the interruption of the service table and many other issues, about the problem of setting the interrupt needs to see what TI's data ah.

How to set up a EDMA interrupt if you want to set up a frame after acquisition. Open interrupt, configure the EDMA parameter.
Two methods: (1) using the BIOS interrupt scheduling, so directly specify the EDMA Interrupt service function, in the Interrupt Service function call API to determine which channel is interrupted. (2) Do not use the BIOS, so that you need to maintain the interrupt vector table, on which ver.asm, in the inside to change the better.
In this regard, a few CCS comes with example.