Does avm_m1_writedata [] have the same meaning as avm_m1_writedata [31: 0] And avm_m1_byteenable = 4' b0011?

Address: http://www.cnblogs.com/oomusou/archive/2008/11/20/sopc_byteenable.html

 

Abstract
When developing a mater IP address, we can determine the degree of parallelism of the data bus, or determine which bytes are valid through byteenable. But are these two methods the same?

Introduction
Why is there such a demand first?

The reason is that the cpu Of the nio ii is 32 bit, so if all IP addresses are 32 bit, the world is peaceful, everything is everything,Because the data bus of the SDRAM in de2/DE2-70 is 16 BitAlthough aveon bus provides a dynamic bus sizing mechanism, render manager master and Server Load balancer have different data bus levels. The system can automatically handle the problem by using the system, we don't have to worry about it, but aveon bus also made it clear in spec that when the 32-bit master crashes to 16-bit slave,Requires two CLK Processors. That is to say, if the data bus of our IP address is 32 bit, it takes two clks to connect to the SDRAM.

Because de2 only has a small amount of SDRAM, so there is no good way to solve, but because the DE2-70 has two hundred 16 bit SDRAM, then the same is different, that is to say,We can merge the two SDRAM databases into a 32-bit SDRAM, so that the 32-Bit Memory input requires one CLK !!

32-bit data should be written into the SDRAM in one CLK, using the concurrency of the hardware,We can have two masters. At the same time, we can import 16 low-bit 32-bit data into 1st slave SDRAM, and 16 high-bit data into 2nd slave SDRAM..

However, there are two methods:
1. Change the data bus of the master IP address to 16 bit., That is, avm_m1_writedata [].
2. The data bus of the master IP address is like 32 bit, but the avm_m1_byteenable, That is, avm_m1_writedata [31: 0] With avm_m1_byteenable = 4'b0011.

If the two results are the same, but the question is, which one is to import 32 bit data into the SDRAM in a CLK.

There is no need to worry about the 1st methods. The master and slave are both 16-bit, and the dynamic bus sizing mechanism will not be triggered, and one CLK will be completed.

The typical problem is that the byteenable encryption method is 2nd, and two ideas may appear:
1. The byteenable action is triggered before the master node enters the aveon bus. Therefore, the master node only has 16-bit slaves into the bus,Slave certainly only needs one CLK..
2. the byteenable action is triggered before the master node enters the aveon bus. Therefore, the 32-bit slave node of the master node enters the bus, but the bytes whose byteenable is 0 are merged into 0, since it is still 32 bit,Therefore, slave still requires two clks..

The following example shows how to use SignalTap II for observation:

The actual slave code in the master IP address is as follows:

 

Assign Avm_m1_byteenable =   4 ' B0011;
Assign Avm_m1_writedata = { 16 ' H0f0f, fifo_rdq1 };

 

Avm_m1_writedata is 16 bits in height. I intentionally fill in 16 'h0f0f. However, in SignalTap, we can find that avm_m1_writedata has a height of 0000 bits. Although byateenable works well, the difference is:When the master node enters the bus, it can be 32 bits, and the az_data fetch of the SDRAM requires two clks.That is, the second idea is the operation of the aveon bus.

Conclusion
According to SignalTap II, The results of render management are the same. avm_m1_writedata [] and avm_m1_writedata [31: 0] are combined with avm_m1_byteenable = 4' b0011 for the actual operation in aveon bus, there are still some differences. We need to send 32-bit data to 2 Gbit/s in a CLK,You must also use avm_m1_writedata [] to work with two masters. You cannot rely on byteenable..

See also
(Original example) how to access SDRAM in a 32-bit way? (SOC)