Embedded driver Development Sensor---"VIP0 PortA", "VIP0 PORTB", "VIP1 PortA", "VIP1 PORTB", Dvo0 (VOUT1) dvo1 (vout0)

(1) VIP Introduction

(2) VIP circuit diagram

(3) VIP Replacement Acquisition camera input

(4) VIP Driver

---------------------AUTHOR:PKF

---------------------------time:2015-01-07

-----------------------------------qq:1327706646

(1) VIP Introduction

Here VIP is the abbreviation of video in Port, "VIP0 PortA", "VIP0 PORTB", "VIP1 PortA", "VIP1 PORTB", a total of 4 ports

The input data format has yuv422i and yuv420t not small this I and t have what difference yuv420t/yuv420i,

Input data bit width has "8-bit", "16-bit", "24-bit"

The input data mode has

"Non-mux Embedded sync", "Line-mux Embedded sync",

"Pixel-mux Embedded sync", "Non-mux discrete sync"

Example CAMERLINK_DRV.C:

Char *gcameralink_portname[] = {
"VIP0 PortA", "VIP0 PORTB", "VIP1 PortA", "VIP1 PORTB",
};

Char *gcameralink_ifname[] = {
"8-bit", "16-bit", "24-bit",
};

Char *gcameralink_modename[] = {
"Non-mux Embedded sync", "Line-mux Embedded sync",
"Pixel-mux Embedded sync", "Non-mux discrete sync",
};

The input mode is HDMI, SDI,VGA, Output has dvo0 (VOUT1) dvo1 (vout0),

(2) VIP circuit diagram

　　

The HDVPSS module, the high-definition video Process Sub System, is used primarily for video capture, DeInterlacing, Scaler, Up/down sample, graphics, Display, etc., is controlled by VPSS-M3 in the media controller Dula ARM CORTEX-M3 system. Software engineers in the process need to pay attention to the various modules supporting the input format and output format of the data (also note that TI provides a RDK to limit the display Controller matrix connection, if you want to flexibly use this matrix connection, You need to split it yourself, please refer to the macro Mapping in Display Controller driver in hdvpss_userguide.pdf for this section. HDVPSS The overall hardware framework as shown, note the data format.

Playback output:

　　

Playback Interface:Playback interface Support independent output at the same timeTwo-way HD images and a signpost-clear image, where two sources of high-definition images can be selected from two digital interfaces (DVO1 and DVO2, where DVO1 supports HDMI output) and one analog interface (Hdcomp is an internally integrated HD DAC), and the SD output supports a wide range of data formats and a wide variety of video modes. (Note that the DVO1 and HDMI common digital signal line, so HDMI and DVO1 output is identical, hardware engineers in the design of the time especially need attention.) Figure 1 Play Port Application DVO1: The interface data can be directly output digital signal can also be sent to the internal HDMI Transfer phy generated HDMI signal, can support the 10/20/30bit internal and external synchronous data output, can send out HS, VS, FID (Field ID) , AVID (Active Video ID), and other timing signals.        The interface has a separate clock source, the HD_VENC_D_CLK. Hdcomp: The interface is actually an internally integrated HD DAC output interface, the highest support 1080p60, pixel clock is 148.5MHz, its timing parameters are programmable, please refer to HDVPSS source code. The HD DAC also has a separate clock source, the HD_VENC_G_CLK.       It is important to note that the interface supports VBI output. DVO2: The interface features basic and DVO1 the same, it is important to note that the DVO2 port does not have a separate clock source, its clock source can share the DVO1 clock source, but also can share the clock source of the HD DAC, so decided the playback interface can only send two independent high-definition images (mainly in the resolution). （ Note: The dm814x DVO2 clock source in RDK is bound to the HDMI port, if you want HDMI and DVO2 to output different resolutions at the same time, please be careful to modify this part of the content, e2e already have a lot of people asked the question. For specific modifications, please refer to the VPSS M3 side display Controller configuration section codeSD DAC: This interface supports the PAL, NTSC, SECAM and other SD video formats, the output format is also diverse, including composite signal (CVBS), s terminal, component Signal (YPBPR), Euro-scart (RGB) and so on. As with the HD DAC, the interface also supports VBI output. Figure 2 playback Port clock allocation

(3) VIP Replacement Acquisition camera input

Synchronization: Divided into internal and external synchronization

"Non-mux Embedded sync", "Line-mux Embedded sync",
"Pixel-mux Embedded sync", "Non-mux discrete sync"

Note:

• for multi channel mode, due to the inability to share the reference clock, the internal synchronization mode must be used, the specific format can refer to BT656 format . Single channel supports three data formats, namely: YUV444, YUV422, Rgb888;multi Channel only support YUV422 format.
• The acquisition port supports VBI data acquisition;
• For multi channel Mode acquisition, the De-multiplexing module is built into the acquisition port, and the module does not require CPU participation;
• Capture Port Pixel always up to 150MHz, that is, the single channel mode acquisition resolution can reach 1080p60,multi Channel mode acquisition resolution can reach the channel [email protected];
• The RGB2YUV and Yuv2rgb color space conversion module (Csc:colorspace Conversion), scalar module (Zoom range: 1/8x---8x), and the drop-sampling module (yuv422toyuv420) are built into the acquisition module.
• The built-in CSC module matrix coefficients ai/bi/ci and bias Di can be set as shown in.

Pixel Mux:In DM8168 's TRM and TVP5158 data sheets are described in detail, is actually a use of time division multiplexing to reduce the number of data pin method, the following two images (all from the TVP5158 data sheet) to illustrate, are two video signal and four-channel video signal (internal synchronization format, To embed the sync signal, refer to the multiplexing mode of the BT656 format: note: The middle clock seems a bit wrong, two D1 pixel mux mode clock should be 54MHz.   Line Mux:(from DM8168 TRM) is a two-way video signal in line MUX mode.
 

(4) VIP Driver

http://blog.csdn.net/crushonme/article/details/11591839

Http://www.61ic.com/Article/DaVinci/TMS320DM81x/201206/42849.html

HTTP://BLOG.CSDN.NET/ZHOUZHUAN2008/ARTICLE/DETAILS/8609110 Multi-core communication

Http://www.deyisupport.com/question_answer/dsp_arm/davinci_digital_media_processors/f/39/t/75959.aspx ti viport A , b simultaneously collect

Http://3y.uu456.com/bp-6ae1bd59ad02de80d4d840b1-6.html

http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/t/218132 Ti

http://wenku.baidu.com/link?url=- Ggjadxxwtiwihjb52um9ozcsr6myskd8piwkv3q6lw7sqngodurt18yldy9hencfdsxsz5s7ss81o-t5gsjo9ivvvxv7lm4yk0dzhlxmcy

Embedded driver Development Sensor---"VIP0 PortA", "VIP0 PORTB", "VIP1 PortA", "VIP1 PORTB", Dvo0 (VOUT1) dvo1 (vout0)