Embedded (Embedded System) Notes--cortex-m3 Introduction and Basics (bottom)

With the study in the class, I would like to record each lesson, for reference, to feed the reader. Since I am in the English class, I will give the key terms in English, and even some content directly in English.

The content of this introduction is still about the basic content of cortex-m3, relative to the previous article, the content of the introduction is more specific and detailed.

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12. Introduction to Registers

Name (for people)		Mnemonic (in code)	Alias (in code)	Detailed Introduction	Note	Related directives
Low Register		R0~r7		Can be used by all instructions Includes thumb instruction (16-bit) and Thumb-2 instruction (32-bit)	Reset does not reset zero
High Register		R8~r12		Can only be used by the Thumb-2 instruction (32-bit)
Stack Pointer		R13	Msp (MAINSP)	The default stack pointer, in OS kernel, Interrupts and Privilege mode use	You can use only one This depends on the current permissions	PUSH POP
			Psp (PROCESSSP)	The stack pointer used in user mode
Link Register		R14	Lr	After the function is called, the address returned		BL func BX LR
Program Counter		R15	Pc	Point to the instruction memory that should be executed	PC always points to Position of current instruction +4 (The detailed principle does not know)
Special Registers	Program Status Register	Psr	Apsr (application)	Consists of 5 values (N, Z, C, V, Q), Each one, corresponding to psr[31~27]	The remaining bits of the PSR are empty. Attention: IPSR, EPSR Read Only	MRS Msr Attention: These two instructions are unable to User Mode Called in
			Ipsr (Interrupt)	Consists of 3 values (ici/it, T, ici/it), corresponding to psr[26:25], psr[24] and psr[15:10 respectively)
			Epsr (execution)	Contains 1 values (Exception number), corresponding psr[8:0]
	Interrupt Mask Register	Primask		1-bit, set to 1 indicates: Allow NMI and hard fault, rest interrupt mask Often used in timing scheduling to temporarily ignore certain interrupts	Default is 0 Indicates no mask
		Faultmask		1-bit, set to 1 indicates: Only NMI allowed, remaining interrupt mask (ignore) Often used by OS kernel to clean up a congested mask queue
		basepri	 	9 bit, used to set the mask priority, set to 1 means:
	Control Register	CONTROL		2-bit, CONTROL[1] Indicates the Stack Status: 0 means using the default Stack (that is, MSP), 1 means using the alternate Stack (that is, the PSP). Control[0] indicates Privilege level in Thread mode: 0 means that thread mode is under Privilege mode, 1 indicates that thread mode is under User mode.	If you are in the handler So these two people can only be 0

13. Introduction to Operation mode

---When the processor reset, the default is initialized to thread mode, the permissions are privileged access level.

With the user access level (which must be in thread mode), you cannot access SCS (System Control Space, which is the part of memory that stores configuration registers and debug-related content).

In user access level, you cannot access special registers, which triggers fault exception once you try to access it.

In privileged access level + Thread mode, you can use code to enter the user access level by setting control[0] to 1.

-When a exception appears, the processor automatically switches to privilege state, and when you exit exception, it returns to the status before exception appears. (The processor is determined by the value of control[0] to enter the state of the permission before the interruption, and in the interruption process, it is necessary to privilege mode, do not see control[0] also do not change)

So, if you want to switch from user mode to privilege mode + Thread mode, you should call an interrupt and set the control[0] to 0 in the interrupt.

14. Introduction to Exceptions and interrupts

Exception number	Address Offset	Exception Type	Priority	Function
0	0x00	Not interrupted	-	The interrupt number for the CORTEX-M3 is from 1, which is not interrupted, but is used to store: Starting value of the MSP
1	0x04	Reset	-3 (highest)	Reset
2	0x08	NMI	-2	Non-maskable Interrupt (non-shielded interrupt)
3	0x0C	Hard fault	-1	When any interrupt is caught in disable or mask, the hard fault is triggered
4	0x10	Mem Manage	Settable	This interrupt is triggered when access to inaccessible memory is available
5	0x14	Bus fault	Settable	When the prefetch instruction is abort (Inst bus), or if the data is obtained incorrectly, the
6	0x18	Usage fault	Settable	When an invalid instruction or an invalid state transition is encountered (for example, to switch to arm State in cortex-m3), it triggers
7-10	0x1c-0x28	-	-	Reserved
11	0x2C	Svc	Settable	System Service call via SVC instruction
12	0x30	Debug Monitor	Settable	-
13	0x34	-	-	Reserved
14	0x38	Pendsv	Settable	Pendable Request for System Service
15	0x3C	SYSTICK	Settable	System Tick Timer
16-255	0x40-0x3ff	Irq	Settable	IRQ (Interrupt request interrupt) input #0-239

This is the contents of the entire Interrupt vector table (ivt,interrupt vector tables), where the starting address in memory is 0.

In addition, PPT also has a sentence, I did not understand, in this doubt, there is a clear classmate hope please answer! The original text reads as follows:

The base address of the vector table is re-locatable (Set the relocation register in the NVIC); Initially, the base address is 0x0.

15. Instruction set Identifier bit

Only the thumb instruction set is in CORTEX-M3, not all arm processors have only the thumb instruction set. Therefore, in an ARM processor, pc[0] is used to identify the type of instruction being referred to. The reason is simple, the instructions are only 16-bit and 32-bit, that is, 2 or 4 bytes, so pc[0] is always 0 (actually pc[1] may also always be 0, this doubt, understand the students want to be able to answer my doubts). Then, ARM also simply do not look at pc[0], use it to identify the type of instruction.

Therefore, we should always set the pc[0] to 1 in the cortex-m3, which means that the instruction is a thumb instruction, and once set to 0, it will trigger the usage fault if it is referred to as ARM instruction (see table above).

16. Stack (stack) and reset Introduction

Choose which stack, according to the right to automatically select, see the 12th "Register Introduction" in the introduction of R13.

However, can not be manually selected, I have some memory, in doubt.

After reset, the processor reads two items from memory:

Address 0:default value of R13 (MSP)

Address 4:reset vector (the starting address of the startup program)

Originally intended to give a PPT in the picture, but the Linux system upgrade out of the point bug, unable to save the picture, and so back can catch out and then fill up.

17. Introduction of Instruction

Here is a detailed explanation of just a few of the instructions mentioned above

Instruction notation	Usage and explanation	Code instance	Note
MSR <special_reg>, <reg>	Write to Special Register	MSR R0, CONTROL	Read and write to special register Only through register, not through memory Moreover, these two instructions Can be used only under privilege permissions
MRS <reg>, <special_reg>	Read Special Register	MRS CONTROL, R0
PUSH {reglist}	Push the largest numbered register first	PUSH {r0-r7, LR}	PUSH, pop is used by SP Note that pc[0] must be 1.
POP {reglist}	Pop the lowest numbered register first	POP {r0-r7, PC}

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At this point, the basic introduction about CORTEX-M3 is complete. In the next article, we will start with the memory to learn more.

Embedded (Embedded System) Notes--cortex-m3 Introduction and Basics (bottom)