Enable signal synthesis

Generation of enable signals by Quartus II Synthesizer

　　　　

Compare the following code with the comprehensive result (the code is taken from the crazybingo routine ):

always@(posedge clk or negedge rst_n)begin    if(!rst_n)        delay_cnt <= 0;    else if(delay_cnt < DELAY_TOP)        delay_cnt <= delay_cnt + 1‘b1;    else        delay_cnt <= 0;endwire    delay_done = (delay_cnt == DELAY_TOP) ? 1‘b1 : 1‘b0;//-----------------------------------always@(posedge clk or negedge rst_n)begin    if(!rst_n)        led_data  <= 0;    else if(delay_done)        led_data <= led_data + 1‘b1;    else        led_data <= led_data;end

The two necessary conditions for generating the enable signal are:

1. the conditional signal (enable signal) must be determined for the signal triggering the output.

2. When the condition signal is determined as false, the trigger outputs the input in the previous state (that is, the input remains unchanged ).

This is the reason why the two if statements in the Code have different results. The above always block statements cannot generate trigger enabling signals, while the underground block statements can generate, because its logic conforms to the role of the enable signal.

The following is the RTL register transfer level circuit diagram after the above Code is integrated: