Establishing time-preserving time equation and its influence

(Note: This translation from: Http://www.edn.com/design/systems-design/4392195/Equations-and-Impacts-of-Setup-and-Hold-Time)

Before delving into the time equation and its impact, let's take a quick look at what happens to build time and hold time.

Build Time: Established time is defined as the minimum time that must be stabilized before the clock is effectively along, in order for the data to be properly latched. Any violation of this time will result in data capture errors and create time violations.

hold time : Keep time defined as the minimum time that the data must remain stable after the clock has been effectively along. The violation of this time will result in data-locking errors and a retention-time violation.

establish time-keeping time equation

First defines the Clock-to-q delay (tclock-to-q), in a trigger triggered by a rise, the input signal is captured along the rise of the clock, and the corresponding output is generated after a short period of delay (TCLOCK-TO-Q). In order for the trigger to perform the above task correctly, the data on its input must be maintained for a period of time (Tsetup) before the clock rises along (thold). In addition, the clock signal through the small difference of the clock tree is called the Clock Twist (Skew).

From FIG. 1 We can get the equation of establishing time and holding time.

Figure 1 Discussion of 2 triggers

In the above figure, at 0 moments, FF1 handles D2FF2 processing D1. It takes a while for the data D2 to be propagated to the FF2, and it's time to start clocking from the FF1 clock, obviously =tc2q+ Tcomb. In order for the FF2 to properly lock the data, D2 must remain stable for a period of time (Setup) at the D end of the FF2 before the 2nd ascent of the clock tree to the FF2; therefore, in order to meet the established time, the equations are as follows:

tc2q + Tcomb + tsetup≤tclk + tskew-------(1)

To better understand the build time and retention time, you can look at the following sequence diagram:

Fig. 2 Establishing time sequence diagram

To avoid maintaining time violations, the data will need to be maintained for a period of time (hold) after the clock has risen. The equations that satisfy the retention time are as follows:

tc2q + tcomb≥thold + tskew-------(2)

It is easy to see from the above two equations that the positive skew of the clock is good for the time of establishment and vice versa. The effective input window is as follows:

Figure-3 Effective input window

Establish time holding time example analysis

　　Considering the two d triggers of Figure 4, we can calculate the maximum clock frequency of the circuit without timing violation, based on detailed timing information.

　　

Figure-Detailed timing information for 42 d triggers

The clock insertion delay is the same for each D trigger, and it does not constrain the given maximum clock operating frequency. As you can see from the illustration above, it does not violate the hold time constraint. The time of study establishment is:

(Time available for data to travel from FF1 to FF2) ≥ (time needed for data to travel from FF1 to FF2)
TCLK + tskew≥ tc2q + Tcomb + Ts2
tclk + 0.25ns≥0.1ns + 5ns + 3ns
tclk≥7.85ns

The minimum clock cycle is 7.85nsand the maximum frequency is 127.4MHz.

　　As can be seen from the above example, the improvement of the maximum clock frequency can be used in the following 3 ways:

1, reduce the combination of logic delay.

2, if you can, increase the clock twist.

3, with faster D triggers (smaller tc2q and Tsetup).

The influence of clock to Q-end delay on time constraint of establishing time

　　Because the latch circuit inside the trigger is two back-to-back inverter (Figure 5), its IO characteristics are shown in Figure 6.

To facilitate interpretation, suppose that the 0V correspondence logic 0,5v corresponds to logic 1; from FIG. 6, it can be seen that if the input of the back-to-back reverse converter is not the correct 0v,5v, it needs a certain lock-up period to produce a stable inverter output, which is called the clock to the Q-end delay (tclock-to-q).

Fig. 5 latch with back to back reverse device

Figure-6 Reverse device IO features

If the delay is cumulative between triggers, a data signal may occur along the miss of the desired captured clock.

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