Experiment 5-Code Converter Experiment

Library IEEE; Use IEEE. std_logic_00004.all; Use IEEE. numeric_std.all; entity docoder_3_to_8 is port (a, B, c, G1, g2a, g2b: In std_logic; Y: Out std_logic_vector (7 downto 0); End entity; architecture RTL of docoder_3_to_8 is signal indata: std_logic_vector (2 downto 0); begin indata <= C & B & A; process (indata, G1, g2a, g2b) isbeginif (G1 = '1' and g2a = '0' and g2b = '0') Then case indata is when "000" => Y <= "11111110 "; when "001" => Y <= "11111101"; when "010" => Y <= "11111011"; when "011" => Y <= "11110111 "; when "100" => Y <= "11101111"; when "101" => Y <= "11011101"; when "110" => Y <= "10111101 "; when "111" => Y <= "01111101"; when others => Y <= "XXXXXXXX"; end case; else Y <= "11111111"; end if; end Process; end architecture RTL;