Exynos 4412 eMMC Configuration and use method

/********************************************************************************* @author?? Maoxiao Hu* @version? V1.0.0* @date??? Feb-2015******************************************************************************* < COPYRIGHT ISE of Shandong UNIVERSITY >********************************************************************************/This article will occasionally improve and correct some minor errors, please go to the Http://www.cnblogs.com/humaoxiao? Reference the latest version. Development Board: Schindler is the 4412 Elite Edition. Uboot:uboot-2014-10. eMMC on the Development Board: Samsung? The klmxgxxemx-b031 capacity 4GB uses the eMMC 5.0 standard. EMMC controller on exynos4412: eMMC4.41 standard used. Reference documentation: See the end of the article.reference documents [2] need to be downloaded to JESD website.
This Samsung EMMC compatible E.MMC 5.0 standard protocol, but 4412 of the EMMC controller is used E.MMC 4.4 standard, such a collocation is not very good for the moment not the table. first, the clock1.1 eMMC Clock SectionThe most basic part is the clock, eMMC supported clocks are divided into a variety of such as 26M 52M HS200 HS400, of course, emmc more high-end supported clock mode is more. How to know eMMC supported clock mode, checkExtended CSD Register [196] Byte, here the B031 chip reading is 0x57, so what is the meaning of each of the 0X57, consult the document [2] 7.4.54 section:?? After the control 0 1 2 4 6 bit 1, that is, support HS400 HS200 hs52-ddr HS52 hs26,4412 can choose any one of the clock mode operation eMMC.? There are also different modes required for clock rate and maximum transfer rate.? 1.2 4412 EMMC Controller section from cm U (Clock Management Unit) module Find the MMC controller clock graph, as follows:??The system power on the default use of Xusbxti clock source, but in the actual use of 24M clock is not enough, so we recommend the manual to select the clock source to sclkmpll_user_t, select the method refer to "Exynos 4412 clock configuration." ?Muxmmc0-3 The registers involved:

? ? Clk_src_fsys

? ? Address: 0x1003c240

? ? Default value: 0x00011111

? ? Value after set: 0x00066666

Registers related to Divmmc0-3 and divmmc0-3_pre:

? ? Clk_div_fsys1 &? Clk_div_fsys2 &? Clk_div_fsys3

? ? Address: 0x1003c544 & 0x1003c548 & 0x1003c54c

? ? Default value: 0x00000000 &?0x00000000 &?0x00000000

? ? Value after setting: 0x09010901 &?0x09010901 &?0x09010901

So in the case of MPLL 800MHz, the first two-frequency and then very frequent, the last eMMC controller clock is 40MHz. However, if the EMMC chip supports HS200 or HS400 high-speed mode, then the controller clock can then be modified.

Second, determine the classAs we all know, eMMC is also graded, from CLASS0 ~ CLASS11, different classes support different command range, not first determine the class will not be able to determine the order eMMC can respond correctly. Check the CSD register of [95:84] Total 12bit. This B031 reading is 0xf5 (11110101) and supports Class0 Class2 Class4 Class5 Class6 Class7 instruction set. Third, determine the supported CMD from the supported class instruction set can be launched by the support of the cmd command,? This can be derived from the B031not supportedThe order of CMD11 CMD20? CMD39? CMD40? cmd53~56. Iv. cmd list? Five, cmd reply format First look at the table above the 4th Column RESP column, on behalf of eMMC reply to the 4412 controller message, they mean as follows: 5.1 R1 reply format? Total 48bit, the highest bit is always 0, followed by 0 from eMMC to the controller, and then [45 : 40] A total of 6bit represents which cmd (0 ~ 63) to reply, then [39:8] A total of 32bit represents the EMMC device state, and then the CRC and the end bit. The meaning of Device status is as follows:? 5.2 R1b Reply format 5.3 R2 reply format R2 used to reply to CMD2 9 10 three commands, when the reply CMD2 10 content is the value of the CID register, when the reply CMD9 the content is the value of the CSR register. 5.4 R3 reply format? 5.5 R4 reply format 5.6 R5 reply format? Six, several commonly used cmd?6.1 CMD0 This command is used to reset eMMC, no reply: 6.2 CMD1 This command gets the EMMC of the OCR register value: here [31] bit is more important, If 1 means the eMMC reset is done,0x40ff8080Reset not completed,0xc0ff8080Reset is complete. 6.3 CMD2 This command to get EMMC CID register value, a total of 128bit,16 bytes: The following is the data read during the actual operation: when compared with the CID register in document (1), it is found to be identical. 6.4 CMD3 This command is used to set the relative address of the EMMC, relative address is for a bus to hook up multiple EMMC prepared, if only one emmc this command does not make much sense. eMMC reply R1 to the controller. 6.5 CMD6 This command is used to set the value of the register in eMMC EXT_CSR: [31:26]: for 0[25:24]: see table below, [23:16]: Index of register to be operated [15:8]: The value to be written to register [7 : 3]: for 0[2:0]: if [25:24] is 00b, then these three bits have the following meanings,6.6 CMD7This command is used to set the state of the eMMC because eMMC is in an idle or Pre_idle state when the EMMC is reset using CMD0, and if data transfer is required, EMMC must be placed in Transfer_state,cmd7. eMMC reply R1 to the controller.6.7 CMD8This command is used to get the value of the EXT_CSD, although the reply is R1, but EXT_CSD's 512-byte value is read and stored in memory, then the user can analyze the various parameters and states that eMMC currently supports. Note that because EXT_CSD is a register group that was introduced after EMMC4, only the EMMC version is judged to be greater than 4, the command is issued to read EXT_CSD. 6.8 CMD13 requires eMMC to send its own status. Seven, operation sequence? eMMC the first need to reset the power, CMD0 implementation, and then EMMC will enter the self-reset busy state, loop send CMD1 to detect busy status, when the busy state is over, eMMC enters the ready state, then sends the CMD2 to authenticate (obtains the CID), then sends the CMD3, then eMMC enters the Stby state, finally uses the CMD7 to enter the transfer state, this time can use the CMD16 to read the single block, CMD17 reads many blocks. The above is the general sequence of operations, including the most critical instructions, of course, can also be inserted in the middle of some not necessary directives, such as CMD6, CMD13 and so on. Detailed status switch diagram see below:??Reference Documentation:[1]? klmxgxxemx-b031 Spec [2] jesd84-b50 (NOTE: EMMC 5.0 standard protocol)

Exynos 4412 eMMC Configuration and how to use