1. Synchronous state Machine

1, the pre-level (such as another chip, PCB cabling, drive interface components) The output of the delay is random, or there may be changes, how to complete the synchronization of the data at the back level?

A: Add RAM or FIFO cache in the Read method after the front level. The key to this approach is the need to have a stack full and empty indicator to manage the reading and reading of the data to prevent data loss.

2, the data has a fixed frame format, how to determine the starting position of the data?

A: 1) add a signal line indicating the starting position of the data, 2) to the asynchronous system, it is often inserted in the data a special code type of synchronization code (synchronization head), the receiving side through the correlation operation detected the synchronization head.

3. The basic clock of cascaded two modules is asynchronous clock domain, how to transmit the data of the pre-stage output accurately to the next level module?

A: 1) at the same frequency: the input data register can be sampled directly with the master clock of the chip, and the synchronization of input data is completed;

2) Asynchronous clock: In particular, when the frequency of two clocks is not generated by the same quartz crystal divider, at least the input is two times the sampling register, but this will read the error data. To avoid errors in asynchronous clocks, we often use the two-port RAM (DPRAM), FIFO cache method to complete the data transfer between asynchronous clock domains.

4. Summary

The circuit that produces a plurality of enable control signals to produce this reliable synchronized clock is the synchronous state machine to be explained below. External asynchronous signals to highly reliable introduction of chip circuits, must meet certain requirements, and must be carefully synchronized processing. No person is prone to circuit hidden trouble, audit workers must be strictly designed, cautious.

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1. Synchronous state Machine