Diode and gate Circuit principle

Source Address: http://blog.csdn.net/gdt_a20/article/details/7229989

For diodes and gate circuits, Vcc = 10v, assuming that 3v and above represent high levels, 0.7 and below represent low levels,

The following is a detailed analysis according to the situation in the picture,

1.ua=ub=0v, the D1,D2 is biased, two diodes will be conduction,

At this point the uy voltage is the diode conduction voltage, that is, the d1,d2 conduction voltage 0.7v.

2. When the Ua,ub is low, it may be assumed that ua = 3v,ub = 0v, then we may start from the D2 analysis,

D2 will be conduction, after the D2 pressure drops will be limited to 0.7v, then D1 because the right side is 0.7v to the left is 3v so will be reversed

Cutoff, so the final Uy is 0.7v, here can also start analysis from D1, if D1 conduction, then Uy should be 3.7v,

At this time D2 will conduction, then D2 conduction, pressure drop will change back to 0.7, the final state uy is still 0.7v.

3.VA=VB=3V, the situation is very good understanding, D1,D2 will be biased, Uy is limited to 3.7V.

Summary (borrowing a definition): Usually after the diode is on, if its cathode potential is constant, Then the anode potential is fixed at a potential higher than 0.7V of the cathode, if the anode potential is constant, then the cathode potential is fixed at Biyang very low 0.7V potential, the effect of the diode after the conduction is called clamp.

Diode and gate Circuit principle