DVI interface application system with tfp401a as the core

Introduction

Currently, analog interfaces have become the standard for desktop display, but the popular PFD display requires completely digitalized interfaces, because for flat display, analog interfaces are completely unnecessary, the digital interface does not have to adjust the clock and phase, and has the advantage of no loss in signal transmission.

With the promotion of digital flat display, the need for digital graphics Connection becomes clearer. The DVI digital video interface standard proposed by the digital display Working Group (ddwg) has solved the above problems well, it is also compatible with traditional VGA and DVI interfaces and is a promising PC video interface standard.

　　1 DVI interface system

DVI transmits digital signals based on tmds (transition minimizeddifferential signaling, minimum difference signal conversion) technology, tmds uses advanced Encoding algorithms to transmit 8-bit data (each subgrade color signal in R, G, and B) the minimum conversion code is 10bit (including the synchronization information, clock information, data de, and error correction). After the DC is balanced, differential signal transmission is better in electromagnetic compatibility than LVDS and TTL. The connection and Transmission Structure of long-distance and high-quality digital signal transmission tmds technology can be achieved using low-cost dedicated cables. 1 is shown in

DVI digital signal transmission uses single link and dual link to transmit data only through channels 1, 2, and 3 shown in Figure 1, the transmission rate can reach 4.9 Gbps, while the dual connection can reach 9.9 Gbps.

　2. Application of DVI interface

Figure 2 shows the common structure of the DVI application system. The DVI interface is the DVI output of the graphics card, and tfp401a is the core of the entire receiving system as the receiving chip of the tmds signal; at2402 is the I2C serial bus memory of ATMEL, used to store edid data.

The tmds link transmitter of DVI interface is generally integrated directly by the display control chip with DVI function into the TDMS transmitter, and the performance can generally meet the dvi1.0 specification; graphics cards with ATI's display control chip as the core, generally, the si1164 chip of the onboard silicon image company is responsible for TDMS signal transmission DVI interface TDMS receiver and signal decoding. This article introduces the tdms receiving system with tfp401a as the core.

2.1 tfp401a Receiver Function Structure

Tfp401a is an TDMS signal receiving chip in the Ti panelbus flat panel display product series. It adopts the advanced 0.18 μm EPIC-5TMCMOS processing technology, using 1.8 V core voltage and 3.3 v I/O voltage, with low noise and low power consumption, its powerpadtm encapsulation technology can ensure the thermal stability of chip operation. It is mainly used for LCD desktop display and can also be used in other high-speed digital video applications.

　The main functions of tfp401a are as follows:

◇ Supports sxga (1280x112, 80Hz) pixels with a clock speed up to MHz;

◇ 24-bit (224 = 16.7 m) real color (1 pixel/clock or 2 pixel/clock );

◇ End impedance matching resistance manufactured by laser precision technology;

◇ Use 4 times oversampling technology; jitter suppression can reach 1 pixel/clock;

◇ It has the jitter Suppression Function of the synchronous line signal.

For details about the specific pin signal of tfp401a, see the data manual. its internal structure and functions are shown in Figure 3. The input rx (2 ~ 0) +-and RXC +-are four tmds signals that are serialized and converted from the host, however, the output signals mainly include odd and even pixel signals (QE [0: 23] And Qo [0: 23]). pixel clock odck, pixel effective de, row/field synchronization (hsyn/vsyn), synchronous detection scdt, etc.

Tfp401a determines the activation status of the link by detecting the status change of the De signal. After the 106 pixel clock, if the de status does not change, it is considered that the link is not activated, in this case, if the system outputs scdt = 0 and scdt = 0, if the de signal is changed twice within the 1024 pixel clock, the link is considered active, in this case, the synchronous detection Indication Signal end (scdt) of the scdt = 1 device can be directly connected to the power control end (PDO) of its output drive, in this way, the chip can automatically manage the power supply of the output Drive Based on the activation of the tmds link, the PD end provided by tfp401a can be used to control the power supply of the entire chip to the system-level power management control end. It is generally not recommended to directly connect to the chip scdt end during design.

2.2 tfp401a output control signal connection

The output control signal of tfp401a is ctl1, ctl2, ctl3, vsync, hsync, and De. Schmidt trigger is generally used as the output drive, to ensure that the low-voltage differential signal can be transmitted to the next-level device, sn74lv14a can be used in the design to achieve the data signal of the output address of this function, which must have sufficient driving capability, this requires driving the wood before the signal processing circuit is passed. The buffer driver chip 74f244 is used to increase the driving capability.

Power Supply and decoupling of 2.3 tfp401a Chip

The System Based on tfp401a is mainly divided into four parts: analog comparator, phase-locked loop (PLL), digital circuit and output signal driver. Among them, the VCO (voltage controlled oscillator) inside the PLL loop is) it is the most sensitive to power fluctuations, and because it needs to provide a benchmark clock for the circuit, the PLL has the highest requirement on power supply; the second is the analog comparator; the digital circuit has relatively low requirements on power supply, however, in the tfp401a Application Guide provided by TI, the power supply uses a unified power supply, and the four power supplies use four Inductors for isolation, which increases the size and weight of the circuit, in addition, the existence of Inductance will also cause interference to the analog circuit. Therefore, we recommend the 4-way power supply method without strict cost control, two tps7333q are used to supply analog and digital circuits, respectively. tps7333q is a low-voltage differential linear voltage regulator circuit with high power supply noise suppression capability, the 3.3 V power supply voltage avdd and pvdd can be provided for the chip, which are the comparator power supply of the analog loop and the PLL Power Supply respectively; ovdd and dvdd are the output drive power supplies of digital circuits and the digital power supplies are separated by analog and digital power supplies, in addition, the circuit with higher power supply requirements can be further smoothed by a series of first-level smaller inductance, which can greatly reduce the circuit volume and improve the power supply quality.

2.4 tfp401a heat dissipation and Copper Coating

Powerpadtm encapsulation technology makes tfp401a highly thermal stable. The chip has a heat dissipation pad of about 25mm at the bottom. It is recommended that the chip be connected to the PCB signal during chip welding, this can provide better EMI performance, and the improved line surge current can suppress power noise more effectively, you can place a through hole pad of about 100 in diameter at the position of the chip heat dissipation pad, and fill the Solder Pad inside it and connect it with the underlying ground copper, in this way, the heat from the chip is transmitted to the back through the solder filled in the through hole and radiating out.

Because tfp401a is usually used in the high-frequency digital analog hybrid signal environment, it is recommended to apply copper on the top and bottom of the PCB to a large area of ground. On the one hand, it can provide a relatively quiet working environment for the chip, on the other hand, it is also conducive to chip cooling. Although tfp401a provides analog, digital, and other four types of power supply pins and ground pins on the chip, but in fact, it is difficult to separate the four ground wires and ground a little bit. Generally, all the grounding pins are connected to the copper fl, and the current trend on the copper fl is opened through a hole, this allows the vast majority of the ground currents of the four types to flow along different paths and finally converge to one place.

2.5 signal cabling and impedance matching

In the DVI link structure, the link clock of XGA can reach 650 MHz at 60Hz field frequency, and the sampling clock inside the chip can reach 615 GHz at this high operating frequency, the chip will become very sensitive to the Circuit Wiring method and Pad Size, rough estimation, 1mm of the wires in the high-frequency circuit about l nh inductance, so that in the 650 MHz link frequency, A 10-mm wire will generate a 40 ohm impedance. Therefore, the signal input pin of the chip should be as close as possible to the line of different signal channels of the DVI interface socket to avoid parallel cabling, the signal line should be isolated by a ground line as much as possible to avoid cross crosstalk between high-frequency signals as much as possible.

At the signal output end of the chip, the clock output foot (odck) can output a square wave signal of up to 86 MHz, the pixel data output pin often works at a frequency higher than 25 MHz. If the pixel data reaches the display control circuit for a long lead, it is necessary to consider the impedance matching problem of the output signal because of the influence of the signal reflection, overspeed, and underspeed plus the surrounding environment. If the matching is not performed, it is very easy to make the control circuit of the display data receiving end appear logic chaos, so in practical application, we should try to string in the matching resistance near the output of each signal of tfp401a, the secondary reflection resistance to suppress the signal is generally 33 ~ Select between 100 Ω, the author selects 33 Ω matching resistance during design, the corresponding signal connection width is 20 mil

　3 VESA standard analysis

Currently, the dual-display interface video card usually uses the 15-pin VGA interface as the main display interface of the system, while the DVI interface is used as the auxiliary display interface when the DVI interface is not connected to the display, the display signal of the secondary channel is disabled to correctly start and use the DVI interface signal. It is usually necessary to master several important VESA display standards.

3.1 DDC Interface Design

DDC (displaydatachannel) shows that the data channel uses ddc2b In the DVI protocol, which is a set of communication standards established on the I2C bus protocol, host) and the display device through the DDC channel to query and transmit edid data, to achieve the correct use of the display device and plug and play with the current main DDC standards include the following:

Ddc1: the original DDC standard, which is a one-way data channel for the display to continuously transmit edid information to the host.
Ddc2: two-way data exchange channel that allows the host to read the display extended display information edid
Ddc2b: allows two-way code exchange between the host and the monitor. The host can send display control commands to the monitor.
Ddc2b +: A two-way data transmission channel that allows the host to control the display. The standard communication bandwidth is wider and can even be connected to other peripherals such as the game lever and mouse.

The key to implementing the core circuit of the DDC interface for the serial I2C bus EEPROM circuit design is to meet the requirements of the I2C bus standard. To ensure the circuit security, 50 ~ 100 Ω throttling resistance

3.2 edid Standard

To implement the DDC interface, we usually need to write the edid data E-DID, which is a data structure with many different variables. It defines the display identifier and various display capabilities to the host, the key to writing edid based on the data transmission protocol between the monitor and the host is to have a clear understanding of the edid data format and extended display ID data, it contains the manufacturer, product serial number, and edid version information of the display device, and points out the display capability supported by the display device, parameters such as resolution, field frequency, frequency range, time sequence of hidden signals, and color coefficient are stored in the dedicated 1 kb eerom memory (that is e-DID data structure is 128 bytes) PC hosts and monitors access data in the memory through the DDC data cable to determine Display Properties (such as resolution, aspect ratio, and so on) of the display.

3.3 HPD (hotplugdetectionl hot swapping Detection

HPD is used to monitor or remove a display device. When the system detects a display device access through HPD, It accesses its edid data through the DDC channel, in order to correctly drive the display device of the new person.

The DVI interface protocol requires the DVI interface to be compatible with the display device to provide edid1.2 or edid2.0 data system startup or when the user modifies the Display Properties of the monitor, query the edid data through the DDC channel. If the connected device has an error or no edid data is detected, the system will not start the DVI interface signal to output the actual application, the edid data should be written to the eeprom of an I2C bus interface, and its clock line (SCL) and data line (SDA) should be written) connect to the 6th and 7 feet of the DVI connector through 1 kΩ pull-up resistor and 16th feet (DVI interface DDC + 5 V power supply end) connected to form the HPD signal of the display device

　4 Conclusion

This paper analyzes the architecture and basic principle of DVI from the perspective of engineering application, and introduces the application design method of a DVI Receiving System Verified by experiment in detail, the purpose is to allow readers to quickly master the communication protocol of DVI and the design of its application circuit, so as to extract video information from the interface and get rid of the Study of complicated hardware principles inside the computer, this allows the DVI interface to develop and use high-quality digital video information as required by users.