JTAG and SWD

Differences between SWD and JTAG and usage

It is the jlink pin diagram given in the segger manual. You can view the relationship between SWD pin and JTAG pin.

I. Differences between SWD and traditional debugging methods

1. SWD mode is more reliable than JTAG in high-speed mode. In the case of a large amount of data, the JTAG download program will fail, but the probability of SWD is much lower. SWD mode can be directly used when JTAG simulation mode is basically used, as long as your simulator supports it. We recommend that you use this mode.

2. SWD simulation can be used when one gpio is missing. This mode supports fewer pins.

3. SWD mode is recommended when the size of the Board is limited. It requires less pins, and of course the PCB space is small! For example, you can choose a very small 5-core terminal with a distance of 2.54 to simulate the interface.

Ii. SWD Mode Supported by the simulator

1. Common simulators on the market support the SWD Mode

(1) jlinkv6 supports SWD simulation mode, which is slow.
(2) jlinkv7 supports the SWD simulation mode, and the speed is significantly improved, 6 times faster than jlinkv6.
(3) jlinkv8 supports SWD simulation mode with a speed of up to 10 MB.
(4) ulink1 does not support SWD mode.
(5) pirated ulink2 provides excellent support for the SWD mode, and the speed can reach 10 MB.
(6) genuine ulink2 supports SWD mode very well and the speed can reach 10 m.

2. Differences on SWD Hardware Interfaces

(1) The hardware interfaces required by jlinkv6 are: Gnd, RST, swdio, and swdclk.
(2) The hardware interfaces required by jlinkv7 are: Gnd, RST, swdio, and swdclk.
(3) The hardware interfaces required by jlinkv8 are VCC, Gnd, RST, swdio, and swdclk. (Note: The actual connections and corresponding experiment results of jlinkv8 are shown below)
(4) ulink1 does not support SWD Mode
(5) hardware interfaces required for ulink2 piracy: Gnd, RST, swdio, and swdclk
(6) The hardware interfaces required by genuine ulink2 are: Gnd, RST, swdio, and swdclk.

It can be seen that only jlinkv8 requires five pins, that is, a VCC pin is added. The advantage is that the RST pin is required for the simulator to simulate the target board, using VCC in the simulator for this function is not very good. Therefore, jlinkv8 selects Gnd only for the target board, but not for VCC. Therefore, I think this mode is the most reasonable. Of course, there is no error in the total Gnd and VCC between the simulator and the target board.

3. SWD mode setting in MDK

In the debugging simulation with J-LINK mode is enough, and in the MDK his function has been done very well, with the standard 20 feet of JTAG download, the speed is very fast, this is generally the case for beginners. However, the SWD method seems to be faster, more convenient, and simpler. It is more advantageous for users with strict requirements on board space and insufficient I/O port resources in the project, the normal JTAG requires 20 pins, while the J-link SWD requires only two wires (pa13/jtms/swdio, pa14/jtck/swclk) this is enough (with 4 power cords), which saves 3 I/O Ports (pa15/jtdi, Pb3/jtdo, pb4/jntrst) for other purposes, in addition, it can save some board space (only four ports are required ).

The following describes some steps, precautions, and precautions for SWD two-line simulation.

The interface connection is as follows: connect jlink 1, 7, 9, and 20 to the VCC, jtms, jtck, And Gnd lines of JTAG on the Development Board respectively!

Next we will show you how to use SWD settings:

Open project option settings:

 

Set the speed to the SWD mode in the settings. You can set the speed according to your actual needs. If the power supply system of your board is not particularly stable, you can set the pattern to 500 K or 1 m if it is large or the simulation line is long. If the environment is good, you can choose 10 M. Of course, the speed will fly.

Remember not to ignore the USB or TCP mode in the lower left. Of course, we use the USB mode, because sometimes the default mode is TCP mode. When we ignore this setting, the simulation will often fail to connect.

 

Below is my own test (using jlink V8)

(1) debugging Based on SW. It is wrong to have 6 feet (13th SWO also needs to be connected) on some materials, SWO does not need to be connected.
(2) There is no big difference in speed between the two methods.
Test again:

(1) There are only four leads, namely, vref, swdio, swclk, And Gnd, instead of 15th, that is, reset.

(2) set the reset bit to autodetect, which can be downloaded and simulated.

(3) If the reset bit is HW reset, the download fails.

(4) The speed is far less than the speed mentioned in the reposted above. It takes about 40 s to erase and write the ucosdemo project. The amount of code for this project is as follows:

Program size: code = 96830 ro-Data = 143650 RW-Data = 1016 Zi-Data = 16440

However, there is a phenomenon that, after a download, it exits, and then enters again (when there is no re-compilation). It seems that there is no erasure or download process, and the time is fast. Maybe this is the reason for the fast time mentioned above?

/// Below from 21 icbbs // http://bbs.21ic.com/icview-127364-1-1.html

Q: I have been playing 103ze on the core board. All the small programs are debugging in ram, and there are only three lines of Gnd swdio swclk (VCC directly connected to the jlink), which is very refreshing. But today I want to try IIS to put a big data in it, so I need to burn it into flash, and find that the progress bar is completed quickly, and then the display fails. I need to search the dog and say that I want to connect to the reset, so I got it... miserable, I have painted all the PCB, and there are only four lines (VCC swdio swclk Gnd). What should I do in the future?

A: You can choose not to connect. Instead, you can use system reset or vect reset in the settings of the MDK simulator. The former applies to a wider range.

//// The reprint is over

JTAG pins can be reused as IO ports, but thus jlink cannot be connected to the chip. There are two solutions:

(1) write another program. Do not reuse the JTAG as an I/O port, and then write the program into the chip using a serial tool;

(2) Set boot0/boot1 to an internal RAM boot, so that the Flash program will not be executed after power-on, so that jlink can "take over" the JTAG pin smoothly.

The purpose of this post is to prepare for the hardware design.

From: http://blog.ednchina.com/czlyzhj/1805761/message.aspx

Additional reading: http://www.iartools.com/Info_ArticleList_Show.asp? ArticleID = 32