Makefile Study Notes

Makefile General Statement ———————

What's in makefile?

Makefile contains five main things: explicit rules, cryptic rules, variable definitions, file instructions, and annotations. 1, explicit rules. Explicit rules explain how to generate one or more target files. This is clearly indicated by the writer of the makefile, to generate the file, the file's dependent file, the generated command.

2, obscure rules. Because our make has an auto-derivation function, the obscure rules allow us to write makefile in a rough and simple way, which is supported by made.

3, the definition of variables. In makefile we want to define a series of variables, the variables are usually strings, this is a bit of your C language macro, when Makefile is executed, the variables will be extended to the corresponding reference position.

4, the document instruction. It consists of three parts, one referring to another makefile in one makefile, like

The C language is the same as the include, and the other is to specify the valid parts of the makefile according to certain circumstances, like

The C language is the same as the precompiled # #, and a command that defines a multiline. About this part of the content that I'll be in

Described in the following sections.

5, comments. In makefile, just the line comment, like the Unix shell script, its comment is the "#" character, which

It's like a "//" in C + +. If you want to use the "#" character in your makefile, you can use a backslash

box to escape, such as: "#". If you need the ' # ' character in Makefile, you should add the backslash ' \# ' to escape

into a normal character.

Finally, it is worth mentioning that the command in makefile must start with the [Tab] key.

Second, the file name of makefile

By default, the make command searches the current directory for file names in order

For "Gnumakefile", "Makefile", "makefile" file, found the explanation of this file. In

Of these three filenames, it is best to use the "Makefile" file name because the first character of this file name is a large

Write, so there is a sense of purpose. It's best not to use "Gnumakefile", this file is GNU's make

Identified by the. There are other make only sensitive to all lowercase "makefile" filenames, but basically, big

Most make supports both the default filenames of "Makefile" and "makefile". Of course, you can use

Other filenames to write makefile, such as:

"Make.linux", "Make.solaris", "Make.aix", etc., if you want to specify a specific makefile,

You can use make's "-F" and "--file" parameters, such as: Make-f Make.linux or makes--file

Make.aix.

Iii. references to other makefile

Using the Include keyword in makefile can include other makefile, much like the C # # #, where the contained file is placed in the current file's containing location. The syntax for include is: include

FileName can be the file mode of the current operating system shell (can be guaranteed with path and wildcard characters)

There can be some empty characters in front of the include, but it must never be the [Tab] key to start. Include and can be separated by one or more spaces. For example, you have a few makefile:a.mk, B.mk, C.mk, and a file called Foo.make, and a variable $ (bar) that contains e.mk and F.MK, then the following statement: include Foo.make *.mk $ ( BAR) is equivalent to:

Include Foo.make a.mk b.mk c.mk e.mk f.mk The Make command starts by looking for the other makefile indicated by the include and placing its contents in its current position. It's like a C + + # include directive. If the file does not specify an absolute path or a relative path, make will look in the current directory first, and if not found in the current directory, make will also be found in the following several directories:

1. If make executes with "-I" or "--include-dir" parameters, then make will look in the directory specified in this parameter.

2, if the directory/include (generally:/usr/local/bin or/usr/include) exists, make will also go to find.

If a file is not found, make generates a warning message, but the fatal error does not occur immediately. It will continue to load other files, and once the makefile has been read, make will retry those not found, or cannot read

File, and if it does not work, make will appear with a fatal message. If you want make to ignore the unreadable files and continue, you can add a minus "-" before the include. such as:-include

It indicates that no error will continue to occur, regardless of any errors in the include process. The related commands that are compatible with other versions of Make are sinclude, and the effect is the same as this one.

IV. environment variable Makefiles

If the environment variable makefiles is defined in your current environment, make makes an action similar to include in the value of this variable. The values in this variable are other Makefile, separated by a space. It's just that, unlike include, the "target" of the makefile introduced from this environment will not work, and if the file defined in the environment variable finds an error, make will ignore it.

But here I still recommend not to use this environment variable, because as long as this variable is defined, then when you use make, all the makefile will be affected by it, this is not what you want to see. In this case, just to tell you that there may be times when your makefile appear strange, then you can see if there is any definition of this variable in the current environment.

V. How make Works

The GNU make operation steps into the following: (think other make is similar) 1, read all the makefile.

2. Read the other makefile that are included in the include. 3. Initialize the variables in the file.

4, deduce the obscure rules, and analyze all the rules. 5. Create a dependency chain for all the target files.

6. Depending on the dependencies, decide which targets to regenerate. 7. Execute the build command.

1-5 steps for the first stage, and 6-7 for the second stage. In the first stage, if the defined variable is used, make will expand it to the location in use. But make does not start all at once, making uses procrastination tactics, and if a variable appears in a dependency rule, the variable will be expanded within it only if the dependency is determined to be used.

Of course, you don't have to be clear about the way you work, but you'll be more familiar with make when you know it. With this foundation, the following sections are easy to read.

Makefile Study Notes