Mips gdb debugging found

(1) If-OS-g is used at the same time, only-OS takes effect.

(2) mips support delay slot, see: http://blog.csdn.net/dogsun88/article/details/7437178

For example:

854f8: 0320f809 jalr t9
854fc: 02202021 move a0, s1

The last time the sub-function is called, the next sentence is to assign s1 to a0. In fact, before calling the sub-function, move a0 and s1 also take effect.

If the-O0 method is used for compilation, the latency slot is not enabled. For example:

Cd670: 1, 10400008
Beqz v0, cd694 <gal_calculateb.pdf + 0x7c>
Cd674: 00000000
Nop

Currently, the-OS optimization is known to enable the delay slot.

(3) During OS optimization, function parameters are transmitted using the a0 a1 a2 register by default.

(4) use disassembly to study the existing optimized Library (the Library debugging information is not visible). Do not use up when using info registers | down. After I find up, the value of info registers has changed.

(5) common instruction sets:

Category	Command	Description
Add number now	Addiu gp, gp,-11040.	Gp = gp-11040
Addition	Addu GP, GP, T9	Gp = GP + T9
Multiplication	Lui GP, 0xa	Gp = 0xa0000
Bitwise AND	AndI v0, V0, 0X4000	V0 = V0 & 0X4000
Load 32-bit	LW v0, 0 (A0)	V0 = memory [A0 + 0]
Save 32-bit	SW v0, 0 (A0)	Memory [A0 + 0] = V0
Load unsigned 8-bit	Lbu A0, 9 (S2)	A0 = memory [S2 + 9]
Value assignment	Li A1, 1	A1 = 1
Variable assignment	Move S1, A0	S1 = A0
Jump with a variable of 0	Beqz v0, 851ac	If (V0 = 0) Jump to 0x851ac
Variable unequal jump	BNE A0, V1, 8544c	If (A0! = V1) Jump to 0x8544c
Function call jump	Jalr T9	Redirect T9 to address