Xilinx FPGA general IO as PLL clock input

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Experiments done on Xilinx ZC7020 's films;

Conclusion

The normal IO cannot be used as the clock input of the PLL, the dedicated clock pin can be;

The normal IO can be connected to the clock input of the PLL via the BUFG, but to modify the PLL settings input CLK option to select "No Buffer";

Specific internal layout assignments can be viewed through Xilinx's FPGA editor,

ZYNQ's clock management is also slightly different from previous films, followed by another introduction, related documents <ug472_7Series_Clocking.pdf>

[Demo1]

//demo1 BUFG Connectmodule Iobuf (input CLK, input rst, output LED); wire clkin_w; BUFG Bufg_inst (. O (clkin_w),//Clock Buffer Output      . I (CLK)//Clock Buffer Input   ); Pll0 u_pll0 (. Clk_in1 (clkin_w),//inch    . CLK_OUT1 (clkout),// out    .       RESET (RST)); //inchAssign led=Clkout;endmodule

PLL the default input front end has a BUFG unit, and two BUFG can not be connected, so the error is reported:

ERROR:NGDBUILD:770-IBUFG ' u_pll0/clkin1_buf ' and BUFG ' bufg_inst ' on net

' Clkin_w ' is lined up in series. Buffers of the same direction cannot be

Placed in series.

Error:ngdbuild:924-input pad net ' clkin_w ' is driving Non-buffer primitives:

[Demo2]

//demo2 Regular IO directly connect to PLLmodule Iobuf (input CLK, input rst, output LED); wire clkin_w;/*BUFG Bufg_inst (. O (Clkin_w),//Clock buffer output. I (CLK)//Clock buffer input);*/pll0 u_pll0 (. Clk_in1 (CLK),//inch    . CLK_OUT1 (clkout),// out    .       RESET (RST)); //inchAssign led=Clkout;endmodule

Normal IO cannot do the input of the PLL directly, so it will report such a mistake:

ERROR:PLACE:1397-A clock IOB/MMCM Clock component pair has been found that

is not placed at an optimal clock iob/mmcm site pair. The Clock IOB

Component <clk> is placed at site <a18>. The corresponding MMCM component

<u_pll0/mmcm_adv_inst> is placed at site <mmcme2_adv_x0y0>. The clock IO can

Use the fast path between the IOB and the MMCM if the IOB are placed on a

Clock capable IOB site that have dedicated fast path to MMCM sites within the

Same clock region. Want to analyze why this problem exists and

Correct it. If This sub optimal condition are acceptable for the This design, you

The Clock_dedicated_route constraint in the. UCF file to demote this

Message to a WARNING and allow your design to continue. However, the use of

This override was highly discouraged as it may leads to very poor timing

Results. It is recommended that this error condition being corrected in the

Design. A List of all the COMP. PINs used in this clock placement rule is

Error:pack:1654-the Timing-driven Placement phase encountered an error.

In the case of UCF, add this constraint:

NET CLK clock_dedicated_route = FALSE;

will still error, in the ZYNQ7000 series, this still can not pass, as follows:

error:physdesignrules:2256-unsupported MMCME2_ADV configuration. The signal

U_pll0/clkin1 on the CLKIN1 pin of MMCME2_ADV comp U_pll0/mmcm_adv_inst with

Compensation mode Zhold must is driven by a clock capable IOB.

Error:pack:1642-errors in physical DRC.

Using normal IO, and then connecting the BUFG to the clock line,

The error will still be reported because the two BUFG are connected:

ERROR:NGDBUILD:770-IBUFG ' u_pll0/clkin1_buf ' and BUFG ' bufg_inst ' on net

' Clkin_w ' is lined up in series. Buffers of the same direction cannot be

Placed in series.

Error:ngdbuild:924-input pad net ' clkin_w ' is driving Non-buffer primitives:

[Demo3]

//dem3 Regular IO with BUFG then connect to the PLL which with "No Buffer" settingmodule Iobuf (input CLK, input rst, output LED); wire clkin_w; BUFG Bufg_inst (. O (clkin_w),//Clock Buffer Output      . I (CLK)//Clock Buffer Input   ); Pll0 u_pll0 (. Clk_in1 (clkin_w),//inch    . CLK_OUT1 (clkout),// out    .       RESET (RST)); //inchAssign led=Clkout;endmodule

The settings for the PLL are as follows,

So the ordinary IO can be used as the PLL clock input, the smooth generation bit;

Clock or the best use of global clock Io, when drawing must note:)

There is no concept of the global clock in the zc702, but with a lot of dedicated clock feet, use the same;

Xilinx FPGA general IO as PLL clock input