Bit band (Bit-band) operation in STM32

Source: Bit band (Bit-band) operation in STM32

After the bit-band operation is supported, a single bit can be read and written using normal load/store instructions. In CM3, there are two zones in which a bit band is implemented. One is the lowest 1MB range of the SRAM area, and the second is the minimum 1MB range of the inside and outside zones. The addresses in these two districts, in addition to being used as normal RAM, have their own "bit-band alias area", which expands each bit into a 32-bit word with the alias area. When you access these words through the bit-band alias area, you can achieve the purpose of accessing the original bits.
The concept of bit-band operation is actually 30 years ago, that is the precedent of 8051 single-chip microcomputer, now, CM3 this ability to evolve, here the bit-band operation is the power of the 8,051-bit addressable area greatly enhanced version.
CM3 uses the following terms to represent the associated address of a bit-band store:
Bit band: Address area that supports bit-band operation
Bit-aliased: access to the alias address is eventually scoped to the access on the band (this midway has an address mapping process)
In the in-place band, each bit is mapped to a word in the alias address area-This is the only LSB valid word. When an alias address is accessed, it is first transformed into a bit-address. For read operations, read one word from the address, then move the desired bit right to the LSB and return the LSB. For write operations, move the bits that need to be written to the left to the corresponding bit sequence number, and then perform an atomic read-and-write process.

The range of two memory areas that support bit-band operations is:

0X2000_0000‐0X200F_FFFF (lowest 1MB in the SRAM area)

0X4000_0000‐0X400F_FFFF (Minimum 1MB in the Sisu area)

To a bit of the SRAM bit band, remembering that the byte address is a and the bit ordinal is N (0<=n<=7), the address of the bit in the alias area is:

aliasaddr=0x22000000+ ((a-0x20000000) *8+n) *4=0x22000000+ (a-0x20000000) *32+n*4

For a bit of the on-chip peripheral bit band, the address of the byte in which it is located is a, and the bit ordinal is N (0<=n<=7), the address of that bit in the alias area is:

aliasaddr=0x42000000+ ((a-0x40000000) *8+n) *4=0x42000000+ (a-0x40000000) *32+n*4

In the formula, "* *" means a word of 4 bytes, "*8" means that there are 8 bits in a byte.

Here is no longer a wordy example:

1. Write 0x3355aacc at address 0x20000000

2. Read the address 0x22000008. This read access reads 0x20000000 and extracts bit 2, with a value of 1.

3. Write 0 at address 0x22000008. This operation will be mapped to the address 0x20000000 "read-write" Operation (atomic), the bit 2 clear 0.

4. Now read the 0x20000000 again and return 0x3355aac8 (Bit[2] cleared 0).

The word with the alias area is only LSB-meaningful. In addition, when accessing a bit with alias area, regardless of the length of the data transfer instruction (Word/half word/byte), the address is aligned to the boundary of the word, otherwise it will produce unpredictable results.

/////////////////////////////////////////////////////////////////bit-band operation for 51 similar gpio control functions//Concrete Realization Idea, refer to <<cm3 authoritative guide >> Fifth chapter (87 page ~92 page).//IO port operation macro definition#defineBitband (addr, Bitnum) ((Addr & 0xf0000000) +0x2000000+ ((addr &0xfffff) <<5) + (BITNUM&LT;&LT;2))#defineMEM_ADDR (ADDR) * ((volatile unsigned long *) (ADDR))#defineBit_addr (ADDR, Bitnum) mem_addr (Bitband (ADDR, Bitnum))//IO port Address mapping#defineGPIOA_ODR_ADDR (GPIOA_BASE+12)//0x4001080c#defineGPIOB_ODR_ADDR (GPIOB_BASE+12)//0x40010c0c#defineGPIOC_ODR_ADDR (GPIOC_BASE+12)//0x4001100c#defineGPIOD_ODR_ADDR (GPIOD_BASE+12)//0x4001140c#defineGPIOE_ODR_ADDR (GPIOE_BASE+12)//0x4001180c#defineGPIOF_ODR_ADDR (GPIOF_BASE+12)//0x40011a0c#defineGPIOG_ODR_ADDR (GPIOG_BASE+12)//0x40011e0c#defineGPIOA_IDR_ADDR (GPIOA_BASE+8)//0x40010808#defineGPIOB_IDR_ADDR (GPIOB_BASE+8)//0X40010C08#defineGPIOC_IDR_ADDR (GPIOC_BASE+8)//0x40011008#defineGPIOD_IDR_ADDR (GPIOD_BASE+8)//0x40011408#defineGPIOE_IDR_ADDR (GPIOE_BASE+8)//0x40011808#defineGPIOF_IDR_ADDR (GPIOF_BASE+8)//0x40011a08#defineGPIOG_IDR_ADDR (GPIOG_BASE+8)//0x40011e08 //IO port operation, only for single IO port!//make sure the value of n is less than 16!#definePaout (n) bit_addr (gpioa_odr_addr,n)//Output#definePAin (n) bit_addr (gpioa_idr_addr,n)//input#definePbout (n) bit_addr (gpiob_odr_addr,n)//Output#definePbin (n) bit_addr (gpiob_idr_addr,n)//input#definePcout (n) bit_addr (gpioc_odr_addr,n)//Output#definePcin (n) bit_addr (gpioc_idr_addr,n)//input#definePdout (n) bit_addr (gpiod_odr_addr,n)//Output#definePdin (n) bit_addr (gpiod_idr_addr,n)//input#definePeout (n) bit_addr (gpioe_odr_addr,n)//Output#definePein (n) bit_addr (gpioe_idr_addr,n)//input#definePfout (n) bit_addr (gpiof_odr_addr,n)//Output#definePfin (n) bit_addr (gpiof_idr_addr,n)//input#definePgout (n) bit_addr (gpiog_odr_addr,n)//Output#definePgin (n) bit_addr (gpiog_idr_addr,n)//input

Bit band (Bit-band) operation in STM32 (RPM)