Four-bit counter

1 Synchronous Reset

Asynchronous reset refers to the reset is not controlled by the clock, but other operations are still related to CLK; synchronous reset means reset signal and clock synchronization.

24-bit counter circuit running flowchart

1) Counter Verilog code

' Timescale 1ns/1ns
Module COUNT4 (OUT,RESET,CLK);
Input RESET,CLK;
Output[3:0] out;
Reg[3:0] out;

Always @ (Posedge CLK)
Begin
if (reset)
out<=0; Synchronous reset
Else
Out<=out+1 ' B1; Count
End
Endmodule

2) testbench test file

' Timescale 1 NS/1 NS
Module COUNT4_VLG_TST ();
/*make a reset that pulses once.*/
Reg Reset=0;
Initial
Begin
#2 reset = 1; Reset
#3 reset = 0; Start Count
#24 reset = 1; Reset
#2 reset = 0; Start Count
#48 reset = 1; Reset
#1 reset = 0; Start Count
#60 reset = 1; Reset
#3 reset = 0; Start Count
#100 $stop;
End
/*make a regular pulsing closk*/
Parameter clk_period = 4;
Reg CLK;
Initial
CLK = 0;
Always # (CLK_PERIOD/2)
CLK = ~CLK;
Wire[3:0] out;
Count4 i1 (. CLK (CLK),. Out),. reset (reset);

Endmodule

Four-bit counter