Fundamentals of Sequential logic circuits

Title: Brief description of establishment time and holding time, drawing instructions

Setup: The minimum time at which data on the data input must remain unchanged before the trigger is TSU on the rising edge of the clock.

Holding time th (hold): The minimum time at which data on the data input must remain unchanged after the trigger has arrived at the rising edge of the clock.

Title: Minimum cycle calculation

TCO: Register update delay. Clock output delay, which is the maximum delay time to trigger to the data output

Minimum clock cycle: Tmin = Tco + Tdata + tsu-tskew. Fastest frequency Fmax = 1/tmin

Tskew = TCLKS–TCLKD.

Title: What is the difference between clock jitter and clock Skew?

Clock jitter: Refers to a temporary change in the clock cycle at a given point on the chip, which may cause the clock cycle to be extended or shortened over different cycles.

Clock Skew: caused by different wiring lengths and loads, resulting in inconsistent timing of the same clock signal reaching the adjacent two sequential units.

The difference: The jitter is generated inside the clock generator, and the crystal oscillator or the internal circuit of the PLL, wiring has no effect on it. Skew is different from the delay of the arrival of the clock rising along different paths caused by different cabling lengths.

Title: What is metastable, what causes it, and how is it eliminated?

Metastable: means that a trigger cannot reach a certain state within a specified time period.

Cause: Because the trigger's tsu and th are not satisfied, when the trigger enters the metastable state, so that the output of the unit can not be predicted, this instability is transmitted along the signal path of the various triggers cascade.

Elimination: Two-level or multilevel register synchronization. In theory, the metastable state can not be completely eliminated, can only be reduced, the general use of two-level trigger synchronization will greatly reduce the probability of metastable occurrence, plus multi-stage trigger improvement is not small.

Title: Synchronous and asynchronous

The difference between synchronous reset and asynchronous reset

A synchronous reset is a reset signal that is activated at any time by the clock edge. An asynchronous reset is a reset signal that is valid and clock independent.

The difference between synchronous and asynchronous logic

Synchronization logic is a fixed causal relationship between clocks. Asynchronous logic is the absence of a fixed causal relationship between clocks

Synchronization circuit and asynchronous circuit difference

Synchronous circuits have a unified clock source, the PLL-divided clock-driven module, because it is a unified clock source driver, so it is synchronous circuit. Asynchronous circuits do not have a unified clock source.

Topic: Talking about the understanding of retiming technology

Retiming is to re-adjust the timing, such as the circuit encountered complex logic, delay is too large, the circuit timing is not satisfied, this time using pipelining technology, in the combination of logic Insert register plus pipelining, operation, area of the idea of speed.

Reprint Please specify source: Ninghechuan (Ning River)

Personal subscription Number: Silicon farming

If you want to receive a personal blog post in time, you can scan the QR code on the left (or long press the QR code) to follow your personal subscription number

Know Id:ninghechuan

Micro Bo Id:ninghechuan

Original address: https://www.cnblogs.com/ninghechuan/p/9800338.html

Fundamentals of Sequential logic circuits