Go Integrated IC design process and tools

IC design process can be divided into two parts: front-end design (also known as logical design) and back-end design (also known as physical design), these two parts do not have a uniform strict boundaries, where the process related to the design can be called back-end design.

The main process of front-end design:

1. Specification Development

Chip specifications, like feature lists, are the design requirements that customers present to chip design companies (known as fabless, fabless), including the specific functional and performance requirements that the chip needs to achieve.

2. Detailed design

Fabless according to the customer's specifications, come up with design solutions and concrete implementation of the architecture, partition module functions.

3. HDL Code

Using the Hardware Description language (Vhdl,verilog HDL, which is typically used by industry companies), the module functionality is described in code, i.e. the actual hardware circuit function is described in HDL language to form RTL (register transfer level) code.

4. Simulation Verification

Simulation verification is to verify the correctness of the coding design, the standard of inspection is the first step to develop specifications. See if the design accurately meets all requirements in the specification. Specification is the design of the correct gold standard, all violations, do not meet the specifications, you need to re-modify the design and coding. Design and simulation validation is a iterative process until the validation results are fully compliant with the specifications. Simulation Verification Tool Mentor Company's Modelsim, Synopsys's VCs, and Cadence's Nc-verilog can be designed to verify RTL-level code, which is generally used by the first-modelsim. This part is called the pre-simulation, then the simulation after the logical part synthesis is called post-simulation.

5, Logic synthesis ――design Compiler

The simulation verifies the logic synthesis through. The result of the logic synthesis is to translate the HDL code of the design implementation into the gate-level grid table netlist. The combination needs to set the constraints, which you want to synthesize the circuit in the area, timing and other target parameters to achieve the standard. The logic synthesis needs to be based on the specific comprehensive library, the area of the basic standard cell of the gate circuit in different library, the timing parameter is not the same. Therefore, the selection of integrated library is not the same, the integrated circuit in the timing, the area is different. In general, after the completion of the synthesis will need to do the simulation verification (this is also known as post-simulation, formerly known as pre-simulation) logic synthesis Tool Synopsys design Compiler, simulation tools Select the above three simulation tools can be.

6, STA

Static Timing Analysis (STA), which is also part of the validation category, is the verification of the circuit in time series, which checks the circuit for the existence of a settling (Setup) and hold time (violation) violation. This is the basic knowledge of the digital circuit, a register when the two timing violations, there is no way to correctly sample data and output data, so the register-based digital chip function will certainly be problematic. The STA tool has Synopsys prime time.

7. Form Verification

This is also a validation category, it is the function (STA is the time series) on the Integrated network table validation. Commonly used is the equivalence check method, with the HDL design after functional verification as a reference, compared with the integrated grid function, whether they are functionally equivalent. This is done to ensure that the circuit functions described in the original HDL are not changed during the logic synthesis process. The formal validation tool has Synopsys formality. The front-end design process is temporarily written here. From the design level, the result of the front-end design is to obtain the chip gate-level grid circuit.

Backend Design Flow back-end process:

1. DFT

Design fortest, testability designs. The inside of the chip often comes with a test circuit, and the purpose of DFT is to consider future tests when designing. A common method of DFT is to insert a scan chain in the design, changing a non-scanning unit (such as a register) into a scanning unit. About DFT, some books have detailed introduction, the control picture is good to understand a little. DFT Compiler for DFT tool Synopsys

2. Layout planning (Floorplan)

Layout planning is to place the Chip macro unit module, in the overall determination of various functional circuit placement position, such as IP module, RAM,I/O pin and so on. Layout planning can directly affect the final area of the chip. Tools for Synopsys's Astro

3. CTS

Clock tree Synthesis, clocks, and simple point is the wiring of the clock. Due to the global command of the clock signal in the digital chip, its distribution should be symmetrical to the various register units, so that the clock from the same clock source to each register, the clock delay difference is minimal. This is why the clock signal needs to be routed separately. CTS tool, Synopsys physical Compiler

4. Cabling (Place & Route)

The wiring here is the normal signal wiring, including a variety of standard units (basic logic gate circuit) between the traces. For example, we usually hear the 0.13um process, or 90nm process, in fact, here the metal wiring can reach the minimum width, from the microscopic point of view is the MOS pipe channel length. Astro of Tool Synopsys

5. Parasitic parameter extraction

Due to the resistance of the wire itself, the mutual inductance between the adjacent conductors, the coupling capacitance inside the chip generates signal noise, crosstalk and reflection. These effects result in signal integrity problems, resulting in signal voltage fluctuations and changes, which can cause signal distortion errors if they are serious. It is very important to analyze the signal integrity problem by extracting parasitic parameters for analysis and verification. STAR-RCXT of Tool Synopsys

6. Physical verification of layout

The physical layout of the complete wiring to verify the function and timing, validation of a lot of projects, such as LVS (Layout Vs Schematic) Verification, simply speaking, is the layout and logic synthesis of the gate-level circuit comparison verification; DRC (Design Rule Checking): Design rules check, check the line spacing, line width and so on to meet the process requirements, ERC (electrical rule Checking): Electrical rules Check, check the short circuit and open and other electrical rules violation; The Hercules actual back-end process for the Synopsys tool also includes circuit power analysis, and the DFM (manufacturability design) problem that arises as the manufacturing process progresses, not to mention here. Physical layout verification is completed in the entire chip design phase, the following is the chip manufacturing. The physical layout is given to the chip foundry (called Foundry) in the Gdsii file format to make the actual circuit on the wafer wafer, and then package and test it to get the chip we actually see.

Reference documents:

[1] The original address. http://bbs.eetop.cn/viewthread.php?tid=424396

[2] Extended reading. liping09003 http://www.eetop.cn/blog/html/24/1174824-type-bbs-view-blog.html

Go Integrated IC design process and tools