How FPGA code is solidified in the internal ROM

I recently went home for a few summer vacation. Although I had to keep learning, I had to look at the theory in a completely isolated computer environment. Today, I will go back and burn the FPGA code into the Rom, and then enable automatic configuration upon power-on. This article is simple and simple, and only serves as my personal record, in case you forget to use the configuration steps in the future. (The image function of the csdn blog is not good yet. It is depressing and can only be recorded in plain text .)

My platform: FPGA chip model: EP1C3T144C8

Software IDE environment: US us II version 9.0

1. First of all, there must be a ready-made project, and the sof file can be generated and burned to the SDRAM in FPGA.

2. Click file-> convert programming files.

3. Select the. JIC file from the programming file type drop-down menu.

4. Select epcs1 for configuration Device

5. File Name is your favorite

6. Click Add device on the Right of Flash loader and select your chip model. Here I select 1C3.

7. Click Add sof data on the right side, add file, and select the corresponding sof file.

8. Generate!

 

After the preceding steps, you can generate a. JIC file, and then burn the file to solidify the program in the Rom. When the progress bar is set to 100%, the program is powered on again or reconfigured to see the effect.