FPGA area Optimization1 for the speed requirement is not very high, we can design the pipeline as an iterative form, thus reuse the same resources of FPGA function.
2 for the control logic is less than the shared logic, the control logic resources can be used to reuse, such as the implementation process of the FIR filter, the multiplier is a shared resource, we can control the resources to implement state machine, thus reusing multipliers, of course, this also sacrificed the area.
3 for modules with similar counting units, the global counter can be used to reduce the area. For example, module a needs a 256 cycle count, module B needs 1000 of the cycle count, then we can design a global counter, the counter number is 10, the first eight bits for module A to use, the entire counter for B use. A more flexible Global counter design can be achieved with a reasonable frequency divider using the PLL.
4 for FPGA internal logic resources are not necessarily all support reset (synchronous reset, asynchronous reset), set and so on. Improper re-location will add resource overhead. such as DSP, RAM only supports synchronous reset. For the shift register does not support reset, the multiplier does not support the position.
5 The optimization of some combinatorial logic can be realized by using reset reset. For example, for a| b We are able to connect a directly to the input of the trigger, and B to the set segment of the trigger, thus saving one or gate.
6 for areas requiring a tighter circuit should try to avoid the reset and set position.
How to optimize the area of FPGA design (logical resource consumption optimization)
