1. Rules of Makefile
The framework of makefile is composed of rules. When the make command executes, it looks for various rules in the makefile file and then runs the rules after parsing the various rules. The basic format of the rule is:
TARGET ...:D epends ...
COMMAND
......
- Target: The goal defined by the rule. Usually the rule is the file name of the last executable file or the target file that is dependent on the executable file, or it can be an action called "pseudo-target";
- DEPENDS: The dependency conditions that are necessary to execute this rule, such as the target file for the executable file, DEPENDS can also be a target, thus forming a nesting between target;
- Command: The commands that the rule executes, that is, the action of the rule. Command commands must start with the TAB key and cannot be replaced with the spacebar.
2. Makefile variable
1. User-defined variables
When you use makefile for rule definitions, users can define their own variables, called user-defined variables. For example:
CC = gcc
CFLAGS =–isub–iadd
TARGET = Cacu
RM = Rm–f
Automatic variables in 2.Makefile
$^: On behalf of all dependent files
[email protected]: represents the target
$<: Represents the first dependent file
3. Other
Use "#" comment in Makefile
In makefile, you can add "@" to the command code before canceling the command echo.
How to use Linux Makefile