Implementation of a half integer Divider

In digital system design, the divider is a basic circuit. The implementation of the divider is very simple. You can use a standard counter or a programmable logic device to implement an integer divider. A divider is usually used to divide a given frequency to obtain the desired frequency. In some cases, the frequency required by the user is not an integer multiple of the frequency clock source. In this case, the Fractional Divider can be used for frequency division.

The basic principle of fractional Division is the pulse throughput counting method: Two integer divider with different division ratios are designed to control the different times of the two division ratios per unit time, to obtain the required fractional division value. For example, if you want to design a divider with a dividing coefficient of 10.1, you can design the divider into 9 times, 10 times, and 11 times, so that the total dividing value is
(9 × 10 + 1 × 11)/(9 + 1) = 10.1

From the characteristics of this implementation method, we can see that because the frequency division value of the divider is constantly changing, the signal jitter obtained after the frequency division is large.
When the Division coefficient is N-0.5 (N is an integer), can control the deduction of pulse time, so that the output is a stable pulse frequency, rather than a n-division, a N-1 frequency.

 

The following is a 2.5-frequency circuit diagram.