In linux, you can view the CPU cache information.

In linux, you can view the CPU cache information.
View CPU cache Information in linux

1. Check the CPU Cache level in Linux.

dmesg | grep cache

The instance result is as follows:

 

Ii. View Cache association methods

View the corresponding folder in/sys/devices/system/cpu /.

For example, to view the number of groups in the level-1 cache of cpu0,

$ cat /sys/devices/system/cpu/cpu0/cache/index0/number_of_sets
$64

For example, you can view the number of rows in a group in the first-level cache of cpu0.

$cat /sys/devices/system/cpu/cpu0/cache/index0/ways_of_associativity
$8

3. view the cache_line size

Taking the cpu level-1 cache of my computer as an example, I learned the size of the level-1 cache of cpu0: 32 k, which contains 64 sets, each with 8 (ways ), the size of each way (cache_line) is calculated as cache_line = 32*1024/(64*8) = 64 bytes. Of course, we can also use the following command to check the cache_line size.

$ cat /sys/devices/system/cpu/cpu0/cache/index0/coherency_line_size

Or

$ cat /proc/cpuinfo

Processor: 0
Vendor_id: GenuineIntel
Cpu family: 6
Model: 60
Model name: Intel (R) Core (TM) i7-4770K CPU @ 3.50 GHz
Stepping: 3
Cpu MHz: 3497.664
Cache size: 8192 KB
Physical id: 0
Siblings: 8
Core id: 0
Cpu cores: 4
Apicid: 0
Initial apicid: 0
Fpu: yes
Fpu_exception: yes
Cpuid level: 13
Wp: yes
Flags: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat limit 36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx limit rdtscp lm limit pebs bts rep_good limit nonstop_tsc kernel pni kernel dtes64 monitor ds_cpl vmx est tm2 ssse3 fma cx16 xtpr pdcm sse4_1 sse4_2 movbe popcnt aes xsave avx lahf_lm abm ida arat kernel vnmi flexpriority PID
Bogomips: 6995.32
Clflush size: 64
Cache_alignment: 64
Address sizes: 39 bits physical, 48 bits virtual

 

Knowing the cpu cache information will help you write efficient programs.

 

(10) The high-speed buffer memory (Cache) is integrated into the modern CPU chip to solve the speed matching problem between the CPU and the main memory.
CPU speed and memory speed, so you need to store common data in a fast place.
High-speed buffer memory (Cache) is configured to solve the problem that the memory speed is significantly different from the CPU speed. The L1 Cache is generally at full speed, and the L2 Cache is generally at half speed.