Java memory model

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3.1 Memory Model Basics

Thread Communication

Message Passing (Explicit), shared memory (implicit)

Thread synchronization

Message passing (implicit), Shared memory (Explicit)

Abstract structure of the 3.1.2 memory model

JMM defines the abstract relationship between each thread and the main memory. Determines when a thread's write to a shared variable is visible to another thread.

Local memory contains cache, write buffers, registers, and other hardware and compiler optimizations.

3.1.3 reordering from source code to instruction sequence

compiler reordering (compiler Level)

Instruction-level parallel reordering (processor-level) instructions the use of parallel techniques makes the instructions appear reordered

Memory system reordering (processor level) The CPU may use a read/write buffer, which makes the load and storage operations appear to be executing in a disorderly order

For compilers, JMM collations prohibit certain types of compilers from being reordered

For processors, the JMM processor collation requires the Java compiler to insert a specific type of memory barrier (fence) instruction when generating a sequence of instructions, prohibiting a particular class type of processor through a memory barrier directive

Re-order.

Classification of 3.1.4 Concurrent programming model

1. Why write buffers are used

Write buffers ensure that the instruction pipeline runs continuously, and it avoids the delay that occurs when the processor pauses to wait for the data to be written to the memory. At the same time, the write buffer is flushed by a batch, and the write buffer is merged

Multiple writes to the same memory address, reducing the memory bus footprint. The write buffers between each processor are isolated from each other. Using write buffers causes the processor to perform a sequence of memory execution and a true sequence of memory execution

of the cause.

2, x86 series because the processor's memory model is strong, this processor only allows the write-read operation to reorder.

3. Memory barrier Directive

The fourth Memory Barrier directive, with the other three all the effects, generally all CPUs support the memory barrier, the other three may not be supported. The barrier needs to flush all the data in the write buffer into memory, so only overhead

Larger.

3.1.5 Happens-before Introduction

1. What is Happens-before

The result of the previous operation is visible to the subsequent operation

2, which Happens-before

1. Program Sequence Rules

2. Monitor Lock rule

3. The Volitale variable rule writes to a volatile variable, happens-before to any subsequent reading of the volatile field.

4, Transmission of

3. One Happens-before rule corresponds to one or more compiler and handler reordering rules.

3.2 Re-ordering

Java memory model