Learning the clock of Apsara stack OK6410

For the OK6410 clock part, we can find the relevant system controller in the system controller from the initi6410 manual:

Power indicates Power-on. After the Power-on is stable, the 12 M crystal oscillator is also stable after the vibration starts. Then, the CPU can obtain a relatively stable clock frequency (12 M). If you want to change the frequency of the crystal oscillator, we will give him a locktime. In locktime, VCO will be able to increase the clock speed through frequency doubling. After locktime is over, the CPU will be able to work under the new frequency.

You can set locktime below

We set it to the default value.

The setting command is as follows:

/* 1. Set LOCK_TIME */

Ldrr0, = 0x7E00F000/* APLL_LOCK */

Ldrr1, = 0x0000FFFF

Strr1, [r0]

Strr1, [r0, #4]/* MPLL_LOCK */

Strr1, [r0, #8]/* EPLL_LOCK */

 

 

 

 

 

 

We can see which clock is provided to which devices

The relationship between peripheral devices corresponding to the specific clock is as follows:

Then we need to set the clock mode. When the CPU clock is different from the memory clock, we need to set the CPU clock mode to asynchronous mode and set the command as follows:

# Define OTHERS 0x7e00f900

@ Set async mode/* When CPU clock! = HCLK, set to asynchronous mode */

Ldrr0, = OTHERS

Ldrr1, [r0]

Bicr1, #0xc0

Strr1, [r0]

In my understanding, this is because this is written in the document

The default value is 0x00, so you do not need to set it. You can change it after testing.

Cyclic latency waits for the CPU to enter asynchronous mode

Loop1:/* wait until the CPU enters the asynchronous mode */

Ldrr0, = OTHERS

Ldrr1, [r0]

Andr1, #0xf00

Cmpr1, #0

Bneloop1

Next we can set the frequency division:

/* SYNC667 */

/* MISC_CON [19] = 0 */

 

# Define ARM_RATIO 0/* ARMCLK = DOUTAPLL/(ARM_RATIO + 1 )*/

# Define HCLKX2_RATIO 1/* HCLKX2 = HCLKX2IN/(HCLKX2_RATIO + 1 )*/

# Define HCLK_RATIO 1/* HCLK = HCLKX2/(HCLK_RATIO + 1 )*/

# Define PCLK_RATIO 3/* PCLK = HCLKX2/(PCLK_RATIO + 1 )*/

# Define MPLL_RATIO 0/* DOUTMPLL = MOUTMPLL/(MPLL_RATIO + 1 )*/

Ldrr0, = 0x7E00F020/* CLK_DIV0 */

Ldrr1, = (ARM_RATIO) | (MPLL_RATIO <4) | (HCLK_RATIO <8) | (HCLKX2_RATIO <9) | (PCLK_RATIO <12)

Strr1, [r0]

The following shows how to configure the clock. The configuration result is that both APLL and MPLL are 532 MB.

/* 2. Configure the clock */

/* 2.1 configure APLL */

/* 2.1.1 set APLL

* 2.1.2 MUXAPLL

* 2.1.3 SYNC667

* 2.1.4 DIVAPLL

*/

# Define APLL_CON_VAL (1 <31) | (266 <16) | (3 <8) | (1 ))

Ldrr0, = 0x7E00F00C

Ldrr1, = APLL_CON_VAL

Strr1, [r0]/* APLL_CON, FOUTAPL = MDIV * Fin/(PDIV * 2 ^ SDIV) = 266*12/(3*2 ^ 1) = 532 MHz */

/* 2.2 configure MPLL */

/* 2.2.1 set MPLL

* 2.2.2 MUXMPLL

* 2.2.3 SYNCMUX

* 2.2.4 SYNC667

* 2.2.5HCLKX2 _ RATIO

* 2.2.6 PCLK_RATIO

*/

# Define MPLL_CON_VAL (1 <31) | (266 <16) | (3 <8) | (1 ))

Ldrr0, = 0x7E00F010

Ldrr1, = MPLL_CON_VAL

Strr1, [r0]/* MPLL_CON, FOUTMPL = MDIV * Fin/(PDIV * 2 ^ SDIV) = 266*12/(3*2 ^ 1) = 532 MHz */

At last, if the lower two digits are 1, select the PLL. If the lower two digits are 0, select the external crystal clock as the clock source. That is why the clock does not need to be initialized, we can also perform the Lighting Program (working below 12 m by default)

/* 3. Select the PLL output as the clock source */

Ldrr0, = 0x7E00F01C

Ldrr1, = 0x03

Strr1, [r0]

Movpc, lr program call return command