Linux LCD Driver (I)-hardware analysis

1. Brief description of the experiment
1. Tutorial Purpose
Learn how to write the driver, configure the LCD driver of S3C2410, and display images in BMP and JPEG formats on the LCD screen.
2. experiment content
(1) analyze the hardware principles of the LCD and LCD controller in the S3C2410 experimental box, find out the corresponding hardware setting parameters, and complete the LCD settings in the xcale experimental box by referring to the LCD settings in the xcale experimental box.

(2) display a BMP image or JPEG image on the LCD.
3. experiment conditions (software and hardware environment)
PC, S3C2410 Development Board, PXA255 Development Board

2. Experiment Principles
1. Analysis of Embedded LCD controller of S3C2410
1.1 S3C2410 LCD Controller
An LCD screen not only needs an LCD driver, but also an LCD controller. Generally, the LCD driver is made together with the LCD glass substrate in the form of cof/COG, while the LCD controller is implemented by an external circuit. The LCD controller has been integrated into the S3C2410, so it is easy to control various types of LCD screens, such as: STN and tftscreen. The characteristics of the S3C2410 LCD controller are as follows:
(1) STN Screen
Three scan modes are supported: 4-bit single scan, 4-bit double scan, and 8-bit single scan.
Supports monochrome, 4-level grayscale, and 16-level grayscale screens
Supports 256-color and 4096-color STN screens (cstn)
Supports resolution of 640*480, 320*240, 160*160, and other types of LCD
(2) tftscreen
Color Palette display modes of monochrome, Level 4 gray, and 256 colors are supported.
Supports 64 K and 16 M color non-palette display modes
Supports resolution of 640*480,320*240 and other types of LCD
For tftscreen control, in addition to sending video materials (VD []) to it, the following signals are essential:
Vsync (vframe): frame synchronization signal
Hsync (vline): synchronous line signal
Vclk: digital-like clock signal
Vden (VM): valid data mark Signal
Because the LCD on the S3C2410 used in this project is a tftscreen, And the tftscreen will be the mainstream application in the future, the next step is to focus on tftscreen control.
Figure 1.1 shows the logic of the LCD controller in S3C2410:

Fig 1.1
Regbank is a register group of the LCD controller. It is used to set parameters of the LCD controller. Lcdcdma is a DMA channel dedicated to the LCD controller. It obtains video data from the system bus and sends it to the LCD screen through vidprcs from VD. At the same time, timegen and lpc3600 are responsible for generating the control sequence required for the LCD screen, such as vsync, hsync, vclk, and vden, and then sending the video MUX to the LCD screen.

1.2 tftscreen Timing Analysis
Figure 1.2 is a typical time series of the tftscreen. Among them, vsync is the frame synchronization signal. Every time vsync sends one pulse, it means that the new one-screen video data is sent. Hsync is the line synchronization signal, and each hsync pulse indicates that the new line of video data starts to be sent. Vden is used to indicate the validity of video data. vclk is used to lock the image clock of video data.
In addition, there must be a return time for both frame synchronization and row synchronization headers and tails. For example, for vsync, the first return time is (vspw + 1) + (vbpd + 1 ), the back-to-sweep time is (vfpd + 1), and hsync is similar. The timing requirement is that it takes time for the CRT display to deflection due to the electron gun, but later it became an actual industrial standard, and the tftscreen appeared later in order to be compatible with the CRT in time series, this control sequence is also used.

Fig 1.2
The LCD on the S3C2410 experimental box is a 3.5-inch tft LCD screen with a resolution of 240*320, which is the timing requirement of the screen.

Fig 1.3
By comparing Figure 1.2 and Figure 1.3, we can easily see that:
Vspw + 1 = 2-> vspw = 1
Vbpd + 1 = 2-> vbpd = 1
Linval + 1 = 320-> linval = 319
Vfpd + 1 = 3-> vfpd = 2
Heat map + 1 = 4-> heat map = 3
Hbpd + 1 = 7-> hbpw = 6
Hozval + 1 = 240-> hozval = 239
Hfpd + 1 = 31-> hfpd = 30
The preceding parameters, except for linval and hozval, are directly related to the screen resolution. The preceding parameters should be used as a reference during actual operations and should not be too biased.

1.3 LCD controller main register function details

Fig 1.4
Linecnt: The current row scan counter value, indicating the number of rows currently scanned.
Clkval: determines the vclk division ratio. The output vclk of the LCD controller is directly obtained from the operating frequency of the system bus (AHB. As a 240*320 tftscreen, make sure that the obtained vclk is within 5 ~ 10 MHz.
Mmode: VM signal trigger mode (valid only for the STN screen and meaningless for the tftscreen ).
Pnrmode: select the current display mode. For tftscreen, select [11], that is, tft LCD panel.
Bppmode: select the color mode. For true color display, select 16 BPP (64 K color) to meet the requirements.
ENVID: enables LCD signal output.

Fig 1.5
The meanings of vbpd, lineval, vfpd, and vspw are shown in the preceding sequence diagram.

Fig 1.6
The meanings of hbpd, hozval, and hfpd are shown in the preceding sequence diagram.

Fig 1.7
The meaning of the heat map has been reflected in the previous sequence diagram.
Mval is only valid for the STN screen and meaningless for the tftscreen.
The meaning of the heat map has been shown in the previous sequence diagram. I will not go into details here.
Mval is only valid for the STN screen and meaningless for the tftscreen.

 
Fig 1.8
Vstatus: indicates the scanning status of the current vsync signal.
Hstatus: The current hsync signal scanning status, indicating the scanning phase of the current hsync synchronization signal.
Bpp24bl: Specifies the order of video data in the display buffer when the 24bpp display mode is set (that is, whether the low position is valid or the high position is valid ). This setting is meaningless for 64 K color display mode of 16bpp.
Frm565: For 16bpp display mode, there are 2 in the form, one is RGB = 5: 5: 5: 1, and the other is. The latter mode is most commonly used. It indicates that red (r) occupies 5 bits and green (g) occupies 6 bits in 16-bit RGB data of 64 K colors, blue (B) occupies 5 bits
Invvclk, invline, invframe, and invvd: As shown in the preceding sequence diagram, we know that the timing output by the cpu LCD controller is a positive pulse by default, while the LCD requires vsync (vframe) and vline (hsync) therefore, invline and invframe must be set to "1", that is, select reverse output.
The functions of invvden, invpwren, and invlend are similar to those in the previous section.
Pwren enables LCD Power Supply Control. In the output signal of the cpu LCD controller, there is a power supply enabling pin LCD _pwren, which is used as the switch signal of the LCD screen power supply.
The enlend is invalid for common tftscreens and can be ignored.
Bswp and hwswp are in bytes or half words (half-word. Since different guis manage framebuffer (display buffer) differently, you need to adjust bswp and hwswp to adapt to Gui when necessary.