Linux Learning Note: "002" arm command line

Processing of instructions

In the CPU, the processing of instructions is generally divided into:

1. Take the instruction stage

The fetch instruction (instruction Fetch,if) stage is the process of taking an instruction from main memory to the instruction register.

A value in the program counter PC that indicates the position of the current instruction in main memory.

When an instruction is removed, the value in the PC is automatically incremented according to the instruction word length:

If the word length instruction, then (PC) +1àpc;

In the case of a double-word instruction, the (PC) +2àpc, and so on.

2. Instruction decoding phase

Once the instruction is removed, the computer immediately enters the instruction decoding (instruction Decode,id) phase.

In the instruction decoding phase, the instruction decoder divides and interprets the retrieved instruction according to the predetermined instruction format, and identifies the different instruction categories and the methods of acquiring the operands.

In the computer with Combinational logic control, the instruction decoder produces different control potentials for different instruction operation codes to form different micro-operation sequences.

In a microcontroller-controlled computer, the instruction decoder uses the instruction opcode to find the entry for the micro-program that executes the instruction and executes from this entry.

In a traditional design, the part of the CPU that is responsible for instruction decoding cannot be changed.

However, in many new CPUs using micro-program control technology, micro-programs are sometimes overridable and can be modified by modifying the CPU of the finished product to change the decoding method.

3. Execution of the instruction phase

After taking the instruction and instruction decoding phase, proceed to the execution instruction (EXECUTE,EX) stage.

This phase of the task is to complete the instructions specified by the various operations, the implementation of the instruction function. To do this, different parts of the CPU are connected to perform the required operations.

For example, if an addition operation is required, the Alu of the arithmetic logic unit is connected to a set of inputs and a set of outputs, and the inputs provide the values to be added, and the output will contain the result of the final operation.

4. Visit and access number stage

Depending on the instruction required, it is possible to access the main memory and read the operand, thus entering the access number (MEMORY,MEM) phase.

The task of this stage is to get the address of the operand in main memory according to the instruction address code, and read the operand from main memory for operation.

5. Results writeback phase

As the last phase, the result writeback (WRITEBACK,WB) phase writes the run result data of the execution instruction phase "back" to some form of storage:

The result data is often written to the internal registers of the CPU for quick access by subsequent instructions;

In some cases, the resulting data can also be written to a relatively slow, but inexpensive, and large-capacity main memory.

Many instructions also change the state of the flags in the program status Word register, which identifies different operating results that can be used to influence the action of the program.

After the instruction is executed and the result data is written back, the computer then takes the next instruction address from the program counter PC, starts a new round of loops, and the next instruction cycle takes the next instruction in sequence, if no unexpected events (such as overflow of results) occur.

What is a command line

In the CPU, the instruction pipelining (instruction pipeline) is a quasi-parallel processing implementation technique which is operated by overlapping instructions when the program executes.

Various parts are processed simultaneously for different instructions, they can simultaneously work on different parts of multiple instructions to improve the utilization of each part and the average execution speed of the instruction.

The processing speed of the pipeline for a single instruction does not increase,

Linux Learning Note: "002" arm command line