Objective:
Basically mastered theThe use of make makes it possible toProgramming on Linux systems.
Environment:
Linux system, or there is a singleLinux server, connected via terminal. Word: thereLinux compilation environment.
Prepare:
Prepare three files:file1.c, file2.c, file2.h
file1.c:
#include <stdio.h>
#include "File2.h"
int Main ()
{
printf ("Print file1$$$$$$$$$$$$$$$$$$$$$$$$\n");
File2print ();
return 0;
}
file2.h:
#ifndef File2_h_
#define File2_h_
#ifdef __cplusplus
extern "C" {
#endif
void File2print ();
#ifdef __cplusplus
}
#endif
#endif
file2.c:
#include "File2.h"
void File2print ()
{
printf ("Print file2**********************\n");
}
Base:
Let's take a first example:
has such a makefile file. (File and makefile in the same directory)
=== makefile start ===
&NBSP;&NBSP;&NBSP;&NBSP;&NBSP;&NBSP;&NBSP;HELLOWORLD:FILE1.O file2.o
GCC file1.o file2.o-o HelloWorld
file1.o:file1.c file2.h
gcc-c File1.c-o FILE1.O
file2.o:file2.c file2.h
Gcc-c File2.c-o FILE2.O
Clean
RM-RF *.O HelloWorld
= = = Makefile End = =
A makefile mainly contains a series of rules, as follows:
A:b
(tab) <command>
(tab) <command>
You must have a tab symbol before each command line .
The makefile file above is intended to compile a HelloWorld executable file. Let us explain in one sentence:
HELLOWORLD:FILE1.O file2.o: HelloWorld relies on file1.o file2.o two target files.
GCC file1.o file2.o-o HelloWorld: compiles the helloworld executable file. -O indicates the target file name you specified.
FILE1.O:FILE1.C: FILE1.O relies on file1.c files.
Gcc-c file1.c-o FILE1.O: compiles the file1.o file. The- c means that gcc compiles only the files that are given to it into the target file, naming it with the file name of the source file but the suffix from ". C" or ". CC" to ". O". In this sentence, you can omit- o file1.o, the compiler generates the FILE1.O file by default, which is the role of-C.
FILE2.O:FILE2.C file2.h
Gcc-c File2.c-o FILE2.O
These two sentences are the same as the last two sentences.
Clean
RM-RF *.O HelloWorld
the *.o and HelloWorld files are deleted when the user types the make clean command .
If you want to compile the CPP file, just change gcc to g++.
Write the makefile file and type the make command directly on the command line to execute the contents of the makefile.
In this step I think you can make up a HelloWorld program.
Previous floor: Using variables
As mentioned above, if you want to compile cpp files, just change gcc to g++. But if there's a lot of gcc in makefile , that's not going to be a problem.
A second example:
= = = Makefile Start===
OBJS = FILE1.O FILE2.O
CC = gcc
CFLAGS =-wall-o-G
HelloWorld: $ (OBJS)
$ (CC) $ (OBJS)-O HelloWorld
file1.o:file1.c file2.h
$ (CC) $ (CFLAGS)-C File1.c-o FILE1.O
FILE2.O:FILE2.C file2.h
$ (CC) $ (CFLAGS)-C File2.c-o file2.o
Clean
RM-RF *.O HelloWorld
= = = Makefile End = =
Here we apply the variable. To set a variable, you simply write the name of the variable at the beginning of the line, followed by a = sign, followed by the value of the variable you want to set. Later you will refer to this variable, write a $ symbol, followed by the variable name enclosed in parentheses.
CFLAGS =-wall-o–g, explain. This is the configuration compiler setting and assigns it to the cfflags variable.
-wall: outputs all warning messages.
-O: optimized at compile time.
-G: indicates compilation of debug version.
This kind of makefile file is relatively simple, but it is easy to find the disadvantage that is to list all C files. If you add a c file, you need to modify the makefile file, which is still troublesome in project development.
One more floor: using functions
Learning here, you might say, it's like compiling a program? There are variables, and there are functions. In fact, this is the programming, but the language is different.
A third example:
= = = Makefile Start = = =
CC = gcc
XX = g++
CFLAGS =-wall-o–g
TARGET =./helloworld
%.O:%.c
$ (CC) $ (CFLAGS)-C $<-o [email protected]
%.o:%.cpp
$ (XX) $ (CFLAGS)-C $<-o [email protected]
SOURCES = $ (wildcard *.c *.cpp)
OBJS = $ (patsubst%.c,%.o,$ (Patsubst%.cpp,%.o,$ (SOURCES)))
$ (TARGET): $ (OBJS)
$ (XX) $ (OBJS)-O $ (TARGET)
chmod a+x $ (TARGET)
Clean
RM-RF *.O HelloWorld
= = = Makefile End = =
function 1:wildcard
Produces a list of all files that end with '. C '.
SOURCES = $ (wildcard *.c *.cpp) indicates that a list of all files ending in. c,. CPP is generated, and then stored in the variable SOURCES.
Function 2:patsubst
Match substitution, there are three parameters. The first one is a pattern that needs to be matched, the second one shows what to replace it with, and the third is a space-delimited list that needs to be processed.
OBJS = $ (patsubst%.c,%.o,$ (patsubst%.cc,%.o,$)) means that all the. SOURCES characters in the file list become . O, form a new list of files, and then deposit The OBJS variable.
%.O:%.c
$ (CC) $ (CFLAGS)-C $<-o [email protected]
%.o:%.cpp
$ (XX) $ (CFLAGS)-C $<-o [email protected]
These commands indicate that all the . C,.cpp are compiled into an . o file.
Here are three more useful internal variables. [email protected] expands to the destination filename of the current rule, $< expands to rely on the first dependent file in the list, and $^ expands to the entire dependent list (removing all duplicate filenames).
chmod a+x $ (TARGET) indicates that the HelloWorld is coerced into an executable file.
Here, I think you have been able to write a relatively simple and common makefile file, all of the above examples assume that all files are in the same directory, not including subdirectories.
So the file is not in a directory can it?
How do I write makefile to generate a static library?
Do you want to get further?
Please listen to tell.
/***************************************/
Original address: http://www.cnblogs.com/goodcandle/archive/2005/11/17/278702.html
Note: Under Windows platform, the command is NMAKE. The file name should be suffixed. Eg:nmake Test.makefile
Linux platform makefile File writing basics (GO)