Makefile Project Management

GNU Make

Linux programmers must learn to use GNU make to build and manage their own software engineering.

GNU make makes it possible to compile and link the entire software engineering with just one command.

Makefile

When make executes, a file named Makefile is required.

The Makefile file describes the compilation, linking, and other rules for the entire project.

including which source files need to compile and how to compile;

Which library files need to be created and how to create them;

How to finally produce the executable file we want.

Makefile (example)

hello:main.o func1.o func2.o     gcc main.o func1.o func2.o-o hellomain.o:main.c    gcc -c main.cfunc1. 0 : func1.c     gcc -c func1.cfunc2.o:func2.c    gcc -c Func2.c.pyony:cleanclean:     rm -F Hello main.o func1.o func2.o

Generates a hello executable file from the main.c func1.c func2.c file.

Makefile (terminology)

rule : Used to describe how to generate one or more target files.

Rule Format :

Targets:prerequisites command

Target: Dependent commands

main.o:main.c gcc -C main.c　　

Note: The command needs to start with the [TAB] key.

Goal

In Makefile, the order of the rules is very important.

There should be only one final goal in the makefile, and the other goals are linked by the whole goal.

So make sure you know what the ultimate goal is.

In general, there may be a lot of goals defined in makefile, but

The goal in the first rule will be established as the ultimate goal.

file name

The make command looks for a project file named Makefile or makefile by default in the current directory.

When the name is not the same, you can specify it by using the Make- F file name .

Pseudo target:

In makefile, those who do not have any dependencies are called "pseudo-targets" (phony targets).

. Phony:cleanclean:    rm -F Hello main.o func1.o func2.o

". Phony "clean" targets are declared as pseudo-targets.

Many *.o files are generated when make is executed, and if you add the above clean, then do clean will delete the specified target file according to the command above.

variables

hello:main.o func1.o func2.o     gcc main.o func1.o func2.o-o Hello

Thinking: If you want to add a dependency to the Hello target, such as: FUNC3.O, how can I modify it?

Answer 1:

func3.o     GCC func3.o -O-Hello

Answer 2:

obj  func3.o$ (obj)    gcc$ (obj)- o Hello

In makefile, there is a system default automation variable

$^ : On behalf of all dependent files

[email protected] : Represents the target

$< : Represents the first dependent file

Cases:

hello:main.o func1.o func2.o     gcc main.o func1.o func2.o-o Hello

Rewrite it into ==>.

hello:main.o func1.o func2.o     gcc $^-o [email protected]

comment and cancel Echo

The content after the "#" character in Makefile is considered as a comment.

@: cancel Echo

hello:hello.c     -O Hello

Makefile Project Management