Memory-Mapped IO space read-write function writeb (), Writew (), Writel ()

Category: Embedded readb (), READW (), Readl () function
Function:
Reads data from the memory-mapped I/O space.
READB Read 8-bit data (1 bytes) from I/O;
READW read 16-bit data (2 bytes) from I/O;
Readl reads 32-bit data (4 bytes) from I/O.

Source file definition Location: arch/$ (Arch)/kernel/io.c

Header file Location: include/asm-$ (ARCH)/io.h
#include <asm/io.h>
unsigned char readb (unsigned int addr)
unsigned char readw (unsigned int addr)
unsigned char readl (unsigned int addr)

Writel and Readl, these two functions are implemented in the operating system layer, with memory protection, to a register or memory address to write a data. Let's talk about Writel:
There are arch/alpha/kernel/io.c in the
188 void Writel (u32 b, volatile void __iomem *addr)
189 {
__raw_writel (b, addr);
191 MB ();
192}

__iomem defined in the Include/linux directory compiler.h, ARM, MIPS are different GCC compilers so there are multiple compiler.h.
__iomem is a feature added in 2.6.9. is used to denote a memory space that points to an I/O. The main purpose is to consider the generality of driver. The representation of the I/O space may be different because of different CPU architectures. When using __iomem, compiler ignores the check of the variable (because it is using void __iomem). But sparse will check it, and when the __iomem pointer is mixed with a normal pointer, some warnings will be emitted.

129 void __raw_writel (u32 b, volatile void __iomem *addr)
130 {
131 Io_concat (__io_prefix,writel) (b, addr);
132}

Io_concat defined in the IO.H in the include/asm-$ (arch) directory
#define IO_CONCAT (A, B) _io_concat (A, B)
#define _IO_CONCAT (b) A # # _ # # B
This code was seen a few days ago, which is the meaning of connecting the strings on both sides, namely AB.

include/asm-$ (Arch)/core_apecs.h
/*
* APECS is the internal name for the 2107X chipset which provides
* Memory controller and PCI access for the 21064 chip based systems.
*
* This file was based on:
*
* DECchip 21071-aa and decchip 21072-aa Core Logic chipsets
* Data Sheet
*
* ec-n0648-72
*
* david.rusling@reo.mts.dec.com Initial Version.
*/
Continue reading the code to see which header is included immediately after defining the __io_prefix. In which of the first article
Search for answers. For your apsec, take a look at the following code snippet (LINUX-2.6.28-RC4)
#undef __io_prefix
#define __io_prefix Apecs
#define APECS_TRIVIAL_IO_BW 0
#define APECS_TRIVIAL_IO_LQ 0
#define APECS_TRIVIAL_RW_BW 2
#define APECS_TRIVIAL_RW_LQ 1
#define APECS_TRIVIAL_IOUNMAP 1
#include <asm/io_trivial.h>

Go to include/asm-$ (arch)/io_trivial.h
__extern_inline void
Io_concat (__io_prefix,writel) (u32 B, volatile void __iomem *a)
{
* (volatile u32 __force *) A = b;
}

is finally through * (volatile u32 __force *) A = b;
To write the data.
The same READL read data is similar to Writel, which is not duplicated here.

# define __force __attribute__ (force) Indicates that the defined variable type can do coercion type conversion, in the sparse analysis, there is no need to report the police information.

(If there is no OS, no MMU, when the board runs bare, we just need a word on everything OK:
* (unsigned long *) addr = value)



IO port mapping and IO memory mapping in Linux
Original address: http://blog.csdn.net/geekster/article/details/11393995
CPU Address Space
(a) The concept of an address

1) Physical Address: The address of the CPU address bus, by the hardware circuit control its specific meaning. A large portion of the physical address is left to memory in the memory bar, but it is often mapped to other storage (such as video memory, BIOS, and so on). After the virtual address in the program instruction passes through the segment map and the page map, the physical address is generated, and the physical address is placed on the address line of the CPU.
Physical address space, part of the physical RAM (memory) used, partly for the bus, which is determined by the hardware design, so in the x86 processor of the three bits address line, the physical address space is 2 of 32 square, that is 4GB, but the physical RAM is generally not up to 4GB, Because there is still a part to be used for the bus (there are many other devices hanging on the bus). In the PC, the low-end physical address is generally used for RAM, high-end physical address to the bus.

2) Bus address: The address line of the bus or the signal generated on the address cycle. The peripheral uses the bus address and the CPU uses the physical address.

The relationship between the physical address and the bus address is determined by the design of the system. On the x86 platform, the physical address is the bus address because they share the same address space-a bit difficult to understand, as described in the "stand-alone addressing" below. On other platforms, conversion/mapping may be required. For example: The CPU needs to access the physical address is 0xfa000 unit, then on the x86 platform, a PCI bus will be generated on the 0xfa000 address access. Because the physical address and the bus address are the same, it is not possible to see with the eyes where the address is being used, either in memory or in a storage unit on a card, or even there is no corresponding memory on the address.

(ii) addressing modalities
1) Peripherals are carried out through the registers on the read-write device, the peripheral register is also called the "I/O port", and the IO port has two ways of addressing: independent addressing and unified programming.

Unified addressing: The IO register (i.e. IO port) in the peripheral interface is treated as the main storage unit, and each end share population uses the address of a memory cell, which is used as an IO address space by a portion of the primary memory, for example, in PDP-11, the highest 4K main memory as the IO device register address. The port occupies the memory address space, which reduces the storage capacity.
Unified addressing is also referred to as "I/O memory", where the peripheral registers are in "memory space" (many peripherals have their own memory, buffers, peripheral registers and memory referred to as "I/O space").
For example, Samsung's s3c2440 is a 32-bit ARM processor, and its 4GB address space is partitioned by peripherals, RAM, and so on:
0x8000 the address of the LED 8*8 dot Matrix
0x4800 0000 ~ 0x6000 0000 SFR (Special Register) address space
0x3800 1002 Keyboard Address
0x3000 0000 ~ 0x3400 0000 SDRAM Space
0x2000 0020 ~ 0x2000 002e IDE
0x1900 0300 CS8900

Independent addressing (separate addressing): The IO address is separate from the storage address, and the i/0 port address does not occupy the address range of the storage space, so that there is another IO address unrelated to the storage address in the system, and the CPU must have an IO instruction (in, out, etc.) and control logic dedicated to the input/output operation. Stand-alone address, the address bus come up with a location, the device is not known to the IO port, or to the memory, so the processor through the MEMR/MEMW and Ior/iow two sets of control signals to achieve the I/O port and memory of different addressing. For example, the Intel 80x86 uses a separate address, CPU memory and I/O are addressed together, that is, the memory portion of the addresses and I/O addresses overlap.
Stand-alone addressing is also known as an I/O port, and the peripheral registers are located in the I/O (address) space.
For the x86 architecture, it is accessed through the In/out directive. PC architecture A total of 65,536 8bit I/O ports, composed of 64K I/O address space, numbered from 0~0XFFFF, there are 16 bits, 80x86 with a low 16-bit address line a0-a15 addressing. Two consecutive 8bit ports can be composed of a 16bit port, 4 consecutive ports composed of a 32bit. The physical address space of the I/O address space and the CPU is two different concepts, such as the I/O address space is 64K, and a 32bit CPU physical address space is 4G. For example, under Intel 8086+redhat9.0, use "More/proc/ioports" to see: