MiS603 Development Board 2.3 state Machine Design

MiS603 Development Team

Date: 20150911

Company: Nanjing mi Lian Electronic Technology Co., Ltd.

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2.3 State Machine Design

State machine is the core component of many digital systems, and is a kind of important sequential logic circuit. It usually consists of three parts: one is the logic circuit of the next state, the second is the sequential logic circuit of the current state of the state machine, and the third is the output combinational logic circuit. In general, state machines have a limited number of states, called Finite state machines (FSM). Because the clock of all the trigger of state machine is triggered by the same pulse edge, it is also called synchronous state machine.

Depending on whether the output signal of the state machine is related to the input of the circuit, it is divided into Mealy type state machine and Moore state machine. The output signal of the circuit is related not only to the current state of the circuit, but also to the input of the circuit, called the Mealy state machine, and the output of the circuit is only the state of each trigger, not affected by the circuit input signal or no input, called the Moore state Machine. The Standard model is as follows:

State machine state transition diagrams, which can also be drawn according to the input and internal conditions. In general, the design of a state machine consists of the following design steps:

? According to the requirements and design principles, determine whether it is a Moore type or mealy type state machine;

? Analyze all States of state machine, choose appropriate encoding method for each state, encode;

? The state transition diagram is plotted according to the state transition relation and output.

? Constructs the appropriate state machine structure, carries on the hardware description to the state machine.

The description of a state machine usually has three methods, called a one-piece state machine, two-segment state machine and three-segment state machine. The description of a state machine typically consists of the following four parts:

1) using the parameter definition statement parameter describes the state machine state name, that is, the state code. There are many methods for state coding, including natural binary coding, One-hot coding, gray code, etc.

2) State storage is realized by using the time-series always block description state trigger;

3) Describe state transition logic using sensitive tables and Case statements (also with If-else equivalent statements);

4) describes the output logic of the state machine.

The following three methods according to the state machine, to compare the advantages and disadvantages of various methods.

? A part-state machine

' Timescale 1ns/1ps

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Create date:10:10:56 09/05/2015

Design Name:

Module Name:detect

Project Name:

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Description: Description of a part-state machine

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Module Detect (

Input clk_i,

Input Rst_n_i,

Input sin,

Output out

);

Reg Out_r;

Status declarations and status codes

reg [1:0] state;

parameter [1:0] s0=2 ' b00;

parameter [1:0] s1=2 ' b01;

parameter [1:0] s2=2 ' B10;

parameter [1:0] s3=2 ' B11;

[Email protected] (Posedge clk_i or Negedge rst_n_i)

Begin

if (!rst_n_i)

state<=0;

Else

Case (state)

S0:

Begin

Out_r<=1 ' B0;

state<= (sin==1)? S0:S1;

End

S1:

Begin

Out_r<=1 ' B0;

state<= (sin==1)? S2:S1;

End

S2:

Begin

Out_r<=1 ' B0;

state<= (sin==1)? S0:S3;

End

S3:

if (sin==1)

Begin

Out_r<=1 ' B1;

state<=s2;

End

Else

Begin

Out_r<=1 ' B0;

state<=s1;

End

Endcase

End

Assign Out=out_r;

Endmodule

A one-piece state machine should be avoided, the writing is only suitable for very simple state machine design, does not conform to the principle of separation of combinational logic and sequential logic, the whole structure code is not clear, do not use maintenance and modification.

? Two-stage state machine

' Timescale 1ns/1ps

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Company:

Engineer:

//

Create date:10:10:56 09/05/2015

Design Name:

Module Name:detect

Project Name:

Target Devices:

Tool Versions:

Description:

//

Dependencies:

//

Revision:

Revision 0.01-file Created

Additional Comments:

//

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Module Detect (

Input clk_i,

Input Rst_n_i,

Input sin,

Output out

);

Reg Out_r;

Status declarations and status codes

reg [1:0] current_state;

reg [1:0] next_state;

parameter [1:0] s0=2 ' b00;

parameter [1:0] s1=2 ' b01;

parameter [1:0] s2=2 ' B10;

parameter [1:0] s3=2 ' B11;

Timing logic: Describing state transitions

[Email protected] (Posedge clk_i or Negedge rst_n_i)

Begin

if (!rst_n_i)

current_state<=0;

Else

current_state<=next_state;

End

Combinatorial logic: Describe the next state and output

[Email protected] (Current_state or sin)

Begin

Out_r=1 ' B0;

Case (Current_state)

S0:

Begin

Out_r=1 ' B0;

Next_state= (sin==1)? S0:S1;

End

S1:

Begin

Out_r=1 ' B0;

Next_state= (sin==1)? S2:S1;

End

S2:

Begin

Out_r=1 ' B0;

Next_state= (sin==1)? S0:S3;

End

S3:

if (sin==1)

Begin

Out_r=1 ' B1;

NEXT_STATE=S2;

End

Else

Begin

Out_r=1 ' B0;

NEXT_STATE=S1;

End

Endcase

End

Assign Out=out_r;

Endmodule

The two-stage state machine uses two always modules to realize the function of state machine, one always adopts synchronous sequential logic to describe state transfer, and the other always uses combinatorial logic to judge state condition transfer. Two-stage state machine is the recommended method of state machine design.

? Three-stage state machine

' Timescale 1ns/1ps

//////////////////////////////////////////////////////////////////////////////////

Company:

Engineer:

//

Create date:10:10:56 09/05/2015

Design Name:

Module Name:detect

Project Name:

Target Devices:

Tool Versions:

Description:

//

Dependencies:

//

Revision:

Revision 0.01-file Created

Additional Comments:

//

//////////////////////////////////////////////////////////////////////////////////

Module Detect (

Input clk_i,

Input Rst_n_i,

Input sin,

Output out

);

Reg Out_r;

Status declarations and status codes

reg [1:0] current_state;

reg [1:0] next_state;

parameter [1:0] s0=2 ' b00;

parameter [1:0] s1=2 ' b01;

parameter [1:0] s2=2 ' B10;

parameter [1:0] s3=2 ' B11;

Timing logic: Describing state transitions

[Email protected] (Posedge clk_i or Negedge rst_n_i)

Begin

if (!rst_n_i)

current_state<=0;

Else

current_state<=next_state;

End

Combinatorial logic: Describing the next state

[Email protected] (Current_state or sin)

Begin

Case (Current_state)

S0:

Next_state= (sin==1)? S0:S1;

S1:

Next_state= (sin==1)? S2:S1;

S2:

Next_state= (sin==1)? S0:S3;

S3:

if (sin==1)

NEXT_STATE=S2;

Else

NEXT_STATE=S1;

Endcase

End

Output logic: Let output out, after register out_r latch output, eliminate burr

[Email protected] (Posedge clk_i or Negedge rst_n_i)

Begin

if (!rst_n_i)

Out_r<=1 ' B0;

Else

Begin

Out_r<=1 ' B0;

Case (Current_state)

S0,s1,s2:out_r<=1 ' B0;

S3:

if (sin==1)

Out_r<=1 ' B1;

Else

Out_r<=1 ' B0;

Endcase

End

End

Assign Out=out_r;

Endmodule

The three-stage state machine uses synchronous sequential logic to describe the state transition in the first always module, and the second always module describes the state transfer law by combining logic, and the third always describes the output of the circuit. Usually let the output signal go through the register cache and then output, eliminate the circuit burr. This kind of state machine is also more respected, mainly because of the convenience of maintenance, combinatorial logic and sequential logic completely independent.

MiS603 Development Board 2.3 state Machine Design