Oracle System interview Test Collate "ask questions when interviewing me, organize a small section" ____oracle

1. What is the tube state and the target State:

The state of the operating system when it is running the management program of the systems. Any instruction, including privileged directives, can be executed in this state.
The configuration refers to the state of the operating system in which the application is running. Only allow applications to access their own memory space.
This ensures that the system is secure when the application is running.

==========================

The state of the CPU belongs to the PSW of the program state character, which is called the privileged state, the system state or the nuclear mentality. Normally, the operating system operates in a tube state, and the CPU can execute the complete repertoire of the instruction system under the control state.
The target State is also called normal or user state, when the machine is in the target State, the program can only execute the non privileged instruction. The user program can only run in the target State.

2.DMA Interrupt (reference:http://baike.baidu.com/view/32471.htm#sub5048463)

DMA principle: DMA (direct Memory access, directly memory access) is an important feature of all modern computers, it allows different speeds of hardware devices to communicate, without the need for a large number of CPU interrupt load. Otherwise, the CPU needs to copy each fragment of data from the source to the register and then write it back to the new location. 　　In this time, the CPU is not available for other jobs. The DMA transfer copies data from one address space to another address space. When the CPU initializes the transfer action, the transfer action itself is implemented and completed by the DMA controller. A typical example is to move a block of external memory to a faster memory area within the chip. Such operations do not delay the processor's work, but can be restarted to handle other tasks. DMA transfer is very important for efficient embedded system algorithms and networks.
In the implementation of DMA transfer, the DMA controller is directly in charge of the bus, so there is a problem of bus control transfer. That is, before the DMA transfer, the CPU to the control of the bus to the DMA controller, and at the end of the DMA transfer, the DMA controller should immediately put the bus control back to the CPU. A complete DMA transfer process must go through the following 4 steps.

1.DMA Request The CPU initializes the DMA controller and emits an operation command to the I/O interface, which makes a DMA request.
2.DMA Response The DMA controller prioritizes and masks the DMA request, and presents the bus request to the bus decision logic. When the CPU is finished executing the current bus cycle, the bus control can be freed. At this point, the Bus award logic output bus response, indicating that DMA has responded, through the DMA controller to notify the I/O interface to start the DMA transfer. 3.DMA Transfer DMA controller obtains the bus control, the CPU immediately hangs or only carries on the internal operation, the DMA controller output reads and writes the command, directly controls the RAM and the I/O interface to carry on the DMA transmission.

Under the control of DMA controller, direct data transfer between memory and external devices is required, and the CPU is not involved in the transfer process. Start by providing the starting position and data length of the data to be transferred.
4.DMA End When the specified mass data transfer is completed, the DMA controller releases the bus control and sends an end signal to the I/O interface. When the I/O interface receives the end signal, on the one hand stop the work of I/O device, on the other hand to the CPU interrupt request, so that the CPU from the state is not involved in free, and perform a section to check the correctness of the DMA transfer operation of the code. 　　Finally, carry out the original procedure with the result and state of the operation. 　　This shows that the DMA transfer mode without direct control of the CPU transmission, there is no interruption of the processing way to retain the scene and restore the scene, through the hardware for RAM and I/O equipment to open a direct transmission of data access, so that the efficiency of the CPU greatly improved. Second, DMA transfer Mode DMA technology, so that peripheral devices can be directly access to memory through the DMA controller, while the CPU can continue to execute the program. So how does the DMA controller and CPU use the memory? The following three methods are usually used: (1) Stop CPU visit, (2) cycle misappropriation; (3) DMA and CPU alternate memory. 3. Virtual Memory

Virtual memory is a technology of computer system memory management. It makes the application think that it has contiguous available memory (a contiguous complete address space), which is usually separated into multiple physical memory fragments, and partly temporarily stored on external disk storage for data exchange when needed.

Virtual Memory. Programs running on a computer need to be executed through memory, and if the program that is executing consumes a large amount of memory or a lot of it, it can lead to memory exhaustion. To solve this problem, Windows uses virtual memory [1] technology, which is to absorb a portion of the hard disk space to act as memory. When memory runs out, the computer automatically calls the hard disk to act as memory to ease memory tension. Windows uses virtual storage for compensation if the computer is running low on random memory (RAM) required to run programs or operations. It combines the computer's RAM with the temporary space on the hard disk. When RAM is running at a slow rate, it moves data from RAM to a space called a paging file. Moving data into a paging file frees up RAM to complete the work. Generally speaking, the larger the RAM capacity of the computer, the faster the program runs. If the speed of the computer slows due to the lack of available RAM space, you can try to compensate by increasing the virtual memory. However, the rate at which the computer reads data from RAM is faster than the speed at which data is read from the hard disk, so expanding RAM capacity (plus memory bars) is the best choice. 4. Compile (reference:http://baike.baidu.com/view/69568.htm)

compile (compilation, compile) 1, the process of generating target program from source program written from source language by compiling program. 2, with the compiler program to generate the action of the target program. Compilation is the high-level language into the computer can be recognized in the 2-language, the computer only know 1 and 0, the compiler program to change the familiar language of 2 into the system. The process of translating a source program into a target program is divided into five stages: lexical analysis, grammatical analysis, semantic inspection and intermediate code generation, code optimization, and target code generation. Mainly for lexical analysis and grammar analysis, also known as source program analysis, the analysis process found that there are grammatical errors, give a hint of information.
5.tcp/ip (refenrence:http://baike.baidu.com/view/7729.htm)

from the aspect of protocol layering model, TCP/IP is composed of four layers: network interface layer, network layer, Transport layer, application layer. the TCP/IP protocol does not fully conform to OSI's seven-layer reference Model, and OSI (open System interconnect) is a traditional open Systems interconnection Reference Model, which is a 7-layer abstract reference Model for communication protocols, each of which performs a specific task. The purpose of the model is to enable various hardware to communicate with each other at the same level. These 7 layers are: Physical layer, Data Link layer (network interface layer), Network layer (network layer), Transport layer, Session layer, presentation layer and Application layer (application layer). The TCP/IP protocol uses a 4-tier hierarchy, and each layer calls its next layer of network to fulfill its needs. Because arpnet designers focus on network interconnection, allow communication subnet (network interface layer) to adopt existing or future protocols, so this level does not provide a dedicated protocol. In fact, the TCP/IP protocol can be connected to any network through the network interface layer, such as a X.25 switched network or an IEEE 802 lan.

6. processes (process) and threads (thread)

A process is a program with a certain independent function about a running activity on a data set, and a process is an independent unit of resource allocation and scheduling for a system. A thread is an entity of a process, the basic unit of CPU scheduling and dispatching, and it is a smaller unit that can operate independently than a process. The thread itself basically does not own system resources, only has a few essential resources in operation (such as program counters, a set of registers and stacks), but it can share all the resources owned by the process with other threads belonging to one process. One thread can create and revoke another thread, which can be executed concurrently between multiple threads in the same process.

The difference between a process and an application is that the application is stored as a static file in storage space, such as the hard disk of the computer system, while the process is a systems resource management entity that is maintained by the operating system under dynamic conditions. 7.Linux Core (reference:http://net.pku.edu.cn/~yhf/lyceum/linuxk/tlk.html)

7.1 Data structure

7.2. ...

Problem Description: Write a function that requires no addition operator (+) to implement the addition operation.

http://blog.csdn.net/lidalong0408/article/details/7576087#