[Original] quickly build unit simulation using system OpenGL

[Original] quickly build unit simulation using system OpenGL

During Simulation of some unit modules, a certain format of data incentives is often required. For example, a unit module that processes TCP packets needs to be constructed to conform to the format of TCP packets. There are roughly two ways to generate incentive based on OpenGL:

Txt file method. Record the required data in txt, which is called during simulation.

Direct synthesis. Directly synthesize the excitation in tb by using Tilde.

The advantages of these two methods are intuitive, but not flexible enough. First, it is difficult to build an incentive data structure when the data structure is complex. Second, when the input protocol of the tested object is changed, the entire system is changed and the tb needs to be checked as a whole.

Building Unit Tests with system OpenGL can overcome these shortcomings and provide other excellent features, such as constrained random incentive generation and test coverage rate analysis.

Based on my practice, I have summarized the solution for Unit Test Based on system OpenGL. I hope to help you and discuss it together.

The following describes how to convert the test tb from the original test tb based on OpenGL to the test tb Based on system pixel. This transition involves four steps:

Modify the tb file type. Changed from. v to. sv.

Add a class to tb. sv.

Write a data-to-signal task in tb. sv.

Call a task and enjoy the test pleasure of sv.

Incentive requirements for unit 1 Simulation

Structure of this module

 

This article focuses on incentive generation, so all output interfaces of the module are omitted. The data input interface signal of this module is as follows:

Signal name

Bit Width)

Description

I _data_valid

1

Level. High indicates that the data is valid.

I _data

64

Data

I _eop_p

1

Pulse, data tail mark

 

The I _data format requirements are as follows:

63: 56

55: 48

47: 40

39: 32

31: 24

23: 16

15: 8

7: 0

Beat1

Msg_type

Pld_len

B

C [47: 16]

Beat2

C [15:0]

Payload

Beat3

Payload

...

...

The fields are described as follows:

Name

Length (byte)

Description

Msg_type

1

Message Type

Pld_len

1

The number of bytes of payload. The minimum value is 6.

B

2

 
C

6

 
Payload

Pld_len

Length depends on pld_len

2. Modify tb

Based on the above input incentive requirements, the sv is used to quickly build the unit simulation incentive.

2.1 modify the tb file type

The original content of msgx_cfg_tb.v is as follows:

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1 module msgx_0000_tb;
2
3 reg clk;
4 reg rst_n;
5 reg I _data_valid;
6 reg [63: 0] I _ data;
7 reg I _eop_p;
8
9 msgx_cfg DUT (
10. clk (clk ),
11. rst_n (rst_n ),
12
13. I _data_valid (I _data_valid ),
14. I _rd1_o_data (I _ data ),
15. I _eop_p (I _eop_p ),
16
17 // other interfaces, omitted
18
19 );
20
21 initial begin
22 clk = 0;
23 forever # 5ns clk = ~ Clk;
24 end
25
26 initial begin
27 rst_n = 0;
28 # 50ns;
29 rst_n = 1;
30 end
31
32 endmodule
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Change the file name to msgx_0000_tb.sv.

2.2 Add a class to tb. sv

Add a class in the msgx_cfg_tb.sv header to generate the data described in "input incentive requirements.

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1 class msg_data_class;
2
3 // declare all fields in data
4 rand bit [7:0] msg_type;
5 rand bit [7:0] pld_len;
6 rand bit [] B;
7 rand bit [47: 0] c;
8 rand bit [7:0] payload [];
9
10 // used to store final data
11 bit [63: 0] data [];
12
13 // Random Constraint
14 constraint legal_payload_size_c {pld_len> 6; payload. size = pld_len ;}
15
16 // customize the pack () function to package fields into a dynamic array of data
17 function void pack ();
18 data ={>>{ msg_type, pld_len, B, c, payload }};
19 endfunction
20
21 // rewrite the class built-in function: post_randomize (), which is automatically called after the class is randomization.
22 function void post_randomize ();
23 pack (); // package
24 endfunction: post_randomize
25
26 endclass
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2.3 Add a task to tb. sv

Now, our msgx_cfg_tb.sv has a class composed of descriptive data, a module. Next, we need to convert the data into interface signals in the module. Write a task in the module to complete the task.

 

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1 module msgx_0000_tb;
2
3 reg clk;
4 reg rst_n;
5
6 reg I _data_valid;
7 reg [63: 0] I _ data;
8 reg I _eop_p;
9
10 // declare class
11 msg_data_class msg;
12
13 msgx_cfg DUT (
14. clk (clk ),
15. rst_n (rst_n ),
16
17. I _data_valid (I _data_valid ),
18. I _rd1_o_data (I _ data ),
19. I _eop_p (I _eop_p ),
20
21 // other interfaces, omitted
22 );
23
24 initial begin
25 clk = 0;
26 forever # 5ns clk = ~ Clk;
27 end
28
29 initial begin
30 rst_n = 0;
31 # 50ns;
32 rst_n = 1;
33 end
34
35 // Add a task
36 task data2signal (msg_data_class msg );
37 @ (posedge clk );
38 I _data_valid <= 1;
39 I _data <= 64 'h0;
40 for (int I = 0; I <msg. data. size; I ++) begin
41 I _data <= msg. data [I];
42 I _eop_p <= I = msg. data. size-1? 1:0;
43 @ (posedge clk );
44 end
45 I _data_valid <= 0;
46 I _data <= 64 'h0;
47 endtask
48
49 endmodule
50
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After writing the data2signal task, you can focus on data layer building during the test case writing process.

2.4 call a task and enjoy the test pleasure of sv.

Let's write the first test case in the module. To facilitate case reproducibility, we encapsulate each case into a task and call each task in the main process, the advantage of doing so is that once there is a change in the later part of the test, the previous case can be easily tested again.

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1 // MAIN PROCESS
2 initial begin
3 test_case1 ();
4 end
5
6 // The first test case
7 task test_case1 ();
8 $ display ("------------- start of test_case1 -------------");
9 msg = new ();
10 wait (rst_n );
11 @ (posedge clk );
12
13 // randomization
14 assert (msg. randomize with {msg_type = 8 'd1 ;});
15
16 // call task: data2signal ()
17 data2signal (msg );
18 $ display ("------------- end of test_case1 -------------");
19 endtask
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In the task test_case1, The assert () statement is used to control the random generation of data packets whose msg_type field is 1. Other fields (the length of pld_len and payload) are constrained by the constraint in msg_data_class. Note: When the constraints in assert () conflict with those in constraint, the simulator will give an alarm. The generated data is uncontrolled and meaningless. Therefore, you must pay attention to the alarm information during simulation, when writing tb data, pay attention to planning and allocating constraints to avoid conflicts.