Registers inside the USRP

Usrp_regs.hpp

#ifndef Included_usrp2_regs_hpp#define included_usrp2_regs_hpp////////////////////////////////////////////////// Define slave bases//////////////////////////////////////////////////////////////////////           #define Router_ram_base 0x4000#define spi_base 0x5000#define i2c_base 0x5400#define gpio_base 0x5800#define readback_base 0x5c00#define eth_base 0x6000#define setting_regs_base 0x7000#def Ine pic_base 0x8000#define uart_base 0x8800#define atr_base 0x8c00//////////////////////// Setting Register offsets//////////////////////////////////////    #define SR_MISC 0//7 regs#define Sr_user_regs 8//2#define sr_time64 10   6#define sr_buf_pool//4#define Sr_spi_core//3#define Sr_rx_front//5#define sr_rx_ctrl0 32 9#define sr_rx_dsp0//7#define sr_rx_ctrL1//9#define SR_RX_DSP1//7#define Sr_tx_front//? #define SR_TX_CTRL 144//6#define SR_TX_DSP 5#define Sr_gpio 184#define sr_udp_sm 192//64#define u2_reg_sr_addr (SR) (Setting_regs_base + (4 * (SR) )) #define U2_reg_router_ctrl_ports u2_reg_sr_addr (sr_buf_pool) + 8//////////////////////////////////////////////// SPI Slave constants//////////////////////////////////////////////////masks for controlling different peripherals# Define spi_ss_ad9510 1#define spi_ss_ad9777 2#define spi_ss_rx_dac 4#define spi_ss_rx_adc 8#define SPI_SS_RX_D B 16#define Spi_ss_tx_dac 32#define spi_ss_tx_adc 64#define spi_ss_tx_db 128#define SPI_SS_ADS62P44-//for usr p2p///////////////////////////////////////////////////Misc control///////////////////////////////////////////// #define U2_reg_misc_ctrl_clock u2_reg_sr_addr (0) #define U2_reg_misc_ctrl_serdes u2_reg_sr_addr (1) #define U2_reg_ MISC_CTRL_ADC u2_reg_sr_addr (2) #define U2_REG_MISC_CTRl_leds u2_reg_sr_addr (3) #define U2_reg_misc_ctrl_phy u2_reg_sr_addr (4) #define U2_REG_MISC_CTRL_DBG_MUX U2_REG_SR_ ADDR (5) #define U2_reg_misc_ctrl_ram_page U2_REG_SR_ADDR (6) #define U2_reg_misc_ctrl_flush_icache u2_reg_sr_addr (7) # Define U2_REG_MISC_CTRL_LED_SRC U2_REG_SR_ADDR (8) #define U2_flag_misc_ctrl_serdes_enable 8#define U2_FLAG_MISC_CTRL _serdes_prbsen 4#define u2_flag_misc_ctrl_serdes_loopen 2#define u2_flag_misc_ctrl_serdes_rxen 1#define U2_FLAG_MISC _ctrl_adc_on 0x0f#define U2_flag_misc_ctrl_adc_off 0x00/////////////////////////////////////////////////// Readback regs////////////////////////////////////////////////#define U2_reg_status readback_base + 4*8#define U2_REG _GPIO_RB readback_base + 4*9#define U2_reg_time64_hi_rb_imm readback_base + 4*10#define U2_REG_TIME64_LO_RB_IMM Readback_base + 4*11#define u2_reg_compat_num_rb readback_base + 4*12#define u2_reg_irq_rb READBACK_BASE + 4*13#define U2 _reg_time64_hi_rb_pps readback_base + 4*14#define U2_reg_time64_lo_rb_pps readback_base + 4*15#endif 

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Registers inside the USRP