[state-Embedded notes] [032] [Exception vector table]

Exception Definitions:

Because of internal or external events that cause the processor to stop working on the work being processed, instead of dealing with these occurrences

Exception type:

1.reset

0x00000000

2.undefine Instructions

0x00000004

3.software Interrupt (Swi)

0x00000008

4.prefetch bort (instruction fetch memory abort) 0x0000000c

5.data Abort (data access memory abort)

0x00000010

6.IRQ (interrupt)

0x00000018 (Note: 0x00000014 not used)

7.fiq (Fast Interrup)

0x0000001c

Exception vectors:

When an exception occurs, the ARM processor jumps to the fixed address of the corresponding exception to execute the exception handler, and this fixed address is called the anomaly vector

Exception Vector table:

A table consisting of seven exception vectors and their processing function jumps is called the anomaly vector table.

Code writing:

1.start. S

/********************************************************************* Name: iboot*d* time: 2015.10.23* Note: 2440 boot (bootloader) of the first-stage boot code (BL1) ********************************************************************/. Text.global _start_start:/*********************************************************************1. Core initialization ********* ***********************************************************//************************************************** 1.1 Set Exception vector table ********************************************************************///exception vector jump Table B Resetldr pc, _undefine_instrucitionsldr pc, _software_interrputldr pc, _prefetch_abortldr pc, _data_abortldr pc, _not_ Useldr pc, _irqldr pc, _frq//exception vector Address Table _undefine_instrucitions:. Word undefine_instrucitions_software_interrput:. Word Software_interrput_prefetch_abort:. Word prefetch_abort_data_abort:. Word data_abort_not_use:. Word not_use_irq:. Word Irq_frq:. Word frq//Exception vector handler/** name: undefine_instrucitions* Description: Handler function when an undefined instruction exception occurs */undefine_instrucitions:nop/** Name: Software_interrput* Description: Handler function when a software interrupt exception occurs */software_interrput:nop/** name: prefetch_abort* Description: The handler function when the instruction prefetch exception occurs */prefetch_abort : nop/** Name: data_abort* Description: handler function */data_abort:nop/** name when data access exception occurs: not_use* Description: Unused function used to take up */not_use:nop/** name: irq* Description: Handler function when an interrupt exception occurs */irq:nop/** name: frq* Description: handler function */frq:nop/** name when a fast interrupt exception occurs: reset* Description: Handler function when reset occurs */RESET:NOP

2.iboot.lds

The architecture of the Output_arch (arm)   output is the entry of the Armentry (_start)   program in _startsections{. = 0x30008000;. = ALIGN (4);. Text: {START.O (. Text) * (. Text)}. = ALIGN (4);. Data: {* (. data)}. = ALIGN (4); bss_start =.;   The starting position of the BSS segment. BSS: {* (. bss)}bss_end =.;   The end position of the BSS segment}

3.Makefile

All:start.oarm-linux-ld-tiboot.lds $^-o iboot.elfarm-linux-objcopy-o binary iboot.elf iboot.bin%.o:%. Sarm-linux-gcc-g-C $^-o [email protected]%.o:%.carm-linux-gcc-g-C $^-o [email protected]clean:rm *.o *.elf *.bin

210 Processor bootloader need to add a header. The verification information needs to be verified at the BL0 stage when the BL1 is copied to the Iram. First, the checksum of the BL1 is computed. The checksum is then compared with the BL1 part of the header. If it matches then copy BL1 to Iram, otherwise terminate.

[state-Embedded notes] [032] [Exception vector table]