System Design Foundation Sixth Week study summary

Chapter Fourth processor architecture section I.Y86Instruction Set ArchitectureFirst, the programmer visible State

Memory

The Y86 program uses virtual addresses to refer to memory locations, and hardware and operating system software unite to translate virtual addresses into actual or physical addresses

Status codeStat

It indicates the overall state of the program execution, indicating whether it is functioning correctly or that an exception has occurred.

TwoY86instructionMOVL class directives

Irmovl,rrmovl,mrmovl,rmmovl

The preceding two letters are in the format of the specified source operand and the destination operand explicitly, the first bit is the source operand, and the second bit is the destination operand.

Four integer operation instructions

Addl plus Subl minus Andl and xorl xor

And they only operate on the register data, setting three condition codes zf\sf\of

Seven Jump commands--Branch Control

JMP Direct Jump Jle (sf^of)| ZF signed number ≤JL sf^of signedje ZF equal / 0 jne ~zf unequal /< /c10> non 0 jge ~ (sf^of) signed ≥JG ~ (sf^of) &~zf signed >

Six conditional delivery Instructions

Cmovle, CMOVL, Cmove, Cmovne, Cmovge, CMOVG

Haltinstruction

The halt instruction stops the execution of the instruction, which causes the processor to stop and the status code to be set to HLT.

Third, byte-level encoding of instructions

Byte encoding must have a unique explanation

Each instruction requires a 1-6 Byte, and the first byte of each instruction indicates the type of instruction.

First byte

The code part of the integer operation is 6, the functional part distinguishes addl,subl,andl, Xorl

The code portion of the branch instruction is 7 .

The code portion of the delivery instruction is 2 .

When you need to indicate that no registers should be accessed, use the ID value 0xF to indicate

Extra bytes required (1) Additional Register indicator bytes

Specify one or two registers, such as RA or rB.

• Without a register operand, such as branch instruction and call instruction, there is no register designator byte.
• An instruction that requires only one register operand (irmovl,pushl,popl) instructs the other register to subscript character to 0xF

（2) Add-on4Byte ConstantsMay include:

1.IRMOVL of the immediate number data 2.rmmol and the mrmovl of the address indicator are offset by 3. the destination address of the branch instruction and the calling instruction

FourY86ExceptionStatus codeStatPossible values for

Stat describes the overall state of the program execution

1. AOK normal Operation 2. The HLT processor executes halt instruction 3. ADR encountered illegal address 4. INS encounters illegal instructions

Section II Logical design and hardware control languageHCLFirst, the logic gate

1. Symbol representation: and &&or | | Not!

2. The logic gate operates only on the number of individual bits, not the entire word.

Second, the combination circuit

Limit:

• Outputs of two or more logic gates cannot be connected together
• Must have no ring

Three, set relationship

The general format for judging set relationships is:

iexpr in {iexpr1,iexpr2,..., IEXPRK}

Iexpr , etc. are all integer expressions.

Four, memory and clock 1.Two types of memory devices for sequential circuits:

(1) clock Register (register): stores a single bit or word.

(2) random access Storage (for short): store multiple words, use the address to choose which word to read / write.

2.y86Processor

It will save the program counter PCwith the clock register, the condition code CC and the program status Stat.

Section IIIY86the sequential implementationFirst, the processing of the organizational stage specific framework is divided into four categories: 1.forOPl(integer and logical operations),RRMOVL(Register-register transfer) andIRMOVL(Immediate number-Register transfer)

2.forRMMOVLand theMRMOVL

3.forPUSHLand thePOPL

4.for jumps,Pagerand theret

TwoSEQHardware StructureSEQDrawing of abstract views:

• The program counter is placed in the register and is located in the lower left corner of the PC.
• The information flows with the line, the direction is first upward then to the right
• Feedback ancestors on the right down
• The processing of all hardware units is done in one clock cycle.
• Light gray squares indicate hardware units
• The control logic block is represented by a gray rounded rectangle.
• The name of the line is indicated in the white ellipse.
• Thin wire for data connections with a width of word length or narrower
• Single bit connection with dashed line

ThreeSEQthe timing

The SEQ implementation consists of a combination of logic and two types of memory devices:

1. Clock Register -- program counter and Condition code Register 2. Random access memory -- register file, instruction memory, and data memory

For the five hardware units mentioned above, it can be divided into two categories:

1. combinational Logic -- instruction Memory 2. Timing :

Condition Code Register- - load data memory only when executing an integer operation instruction - - only in executing rmmovl,PUSHL or call when writing to a register file -- two write ports allow two program registers to be updated per clock cycle. Special registers? 0xF indicates that this port should not perform a write operation.

FourSEQimplementation of the phase1. Taking the finger stage

Take the PC as the first byte and read 6 bytes.

Two logical blocks (separated from the first byte, four bits each)

icode- Instruction Code ifun- instruction function

Three-bit signals (based on icode values)

instr_valid- found illegal directive need_regids- contains register designator byte need_valc- include constant number?

The latter five bytes are the combined encoding of the Register designator byte and the constant number.

2.decoding and writeback phases3.implementation Phase

(1) including the arithmetic / logic unit ALU, the output is ValE.

ALU is often used as an adder

(2) including the condition code register

0, sign, overflow, generate signal SET_CC

4.Visit Stage

Based on Icode,imem_error,instr_valid,dmem_error, the status code Stat is calculated from the result of the instruction execution .

5.UpdatePCStageReference: http://www.cnblogs.com/20135202yjx/p/4888820.html

Experiment Five:

Y86 Writing Program Files

System Design Foundation Sixth Week study summary