Processor Architecture
I. Y86 instruction SET architecture
1.y86 is an instruction architecture (ISA), which is the instruction set of the author yy of the computer system. The goal is to give us a clearer understanding of the ISA.
2.Y86 Instruction Set:
3.y86 exception: Y86 has four different status codes, AOK (normal), HLT (Execute Halt command), ADR (illegal address), and ins (illegal instructions).
Second, HCL
1. Combinational Circuits and HCl Boolean expressions
Combinational circuits: A lot of logic gates make up a net, it can form a computational block.
There are two limitations to building these nets:
① the outputs of two or more logic gates cannot be connected together, otherwise they may cause a contradiction in the signal on the line and may result in an illegal voltage or electrical failure.
② This net must be non-ring.
2. Combination Circuit of byte and HCl integer expression:
Third, the order realization of Y86
1.SEQ: Sequential processor.
On each clock cycle, SEQ executes all the steps required for a complete instruction.
2. Basic stage:
①: Reads instruction bytes from memory, addresses the value of the program counter PC
② decoding: Read up to two operands from register, get Vala or Valb
③ execution: The arithmetic/logic unit either executes the operation specified by the instruction, calculates the valid address of the memory reference, or increases or decreases the stack pointer. The resulting value is Vale
④: Writes data to memory, or reads data from memory, and reads a value of Valm
⑤ write back: Up to two results can be written to the register file
⑥ Update PC: Set the PC as the address of the next instruction
3.SEQ constants:
Iv. references
1. In-depth understanding of computer systems. pdf
2.http://www.mamicode.com/info-detail-1081905.html
3.http://www.tuicool.com/articles/zv6v6n
V. Problems encountered
Unfamiliar with the concept of seq. Later, under the guidance of the students, contact with the previous study of EDA and digital knowledge, has a preliminary understanding of it.
The fifth week Experiment report of information security system design