The "bit" of a single chip microcomputer

Common MCUs are 8-bit, 16-bit, 32-bit, 64-bit, and 4-bit earlier (and, of course, now in use), as for 128-bit? Maybe it's PowerPC, but it doesn't seem to be part of the MCU's range.

So how do we divide this "bit"?

Depends on the width of the internal data bus of the internal data bus width.

There are two types of architectures for MCUs today:

1. von Neumann structure (Von-neumann Architecture) or (Princeton Architecture (Princetion Architecture))

PM (program memory) and DM (Data memory) Two memory share a bus, this bus is the number of bits is the number of single-chip microcomputer.

Example: MSP430

MSP430G2 series is 16-bit RISC CPU, the kernel contains a 16-bit alu, register is also 16-bit, 16-bit address bus, 16-bit data bus is MABW (Memory address bus Width ) equals MDBW (Memory Data Bus Width).

Generally the standard architecture is this, but now more is the improved architecture, there will be PMBW (PROGRM memory Bus Width) greater than DMBW (Data memory buswidth), when MABW is greater than or equal to MDBW.

Example: MSP430

The MSP430F5 series is a 16-bit RISC CPU, but the kernel contains a 16-bit or 20-bit alu, the register is 20 bits, but 16-bit address bus or 20-bit address bus, 16-bit data The bus is MABW greater than or equal to MDBW.

Can this be because the ALU is 20 bits and the register is 20 bits to say that this CPU is a 20-bit CPU? Obviously not, because the front said "bit" depends on the IDBW,MABW change only increased the CPU's addressing range, from the 16-bit 64KB to 20-bit 1MB.

Note: Here said msp430x CPU is Von-neumann architecture improved type for personal view.

2. Harvard Architecture (Harvard Architecture)

In Harvard Architecture, PM and DB are independent, so PMBW (Pragram memory bus width) and DMBW (Data Memory bus width) can be different, or Harvard Architecture is designed for this difference.

Example: PIC 8-bit series

"Instructions and Data on separate busses", which means that PMB and DMB are independent of each other.

"Wide Program Memory Buses (16bit, & 16-bit)", the application Storage bit width (PMW) is divided into 12-bit, 14-bit, and, in the official manual, "12-bit Wide instructions". (pic10f series) This is PMW, at this time we can not say that it is a 12-bit CPU, because DMW is 8 bits, the ALU and the register are 8 bits.

Description: The AW of PMB (addess width) and DMB can be different, not only the two can be different, Pmaw (program Memory address width) and PMW, Dmaw (Data Memory address width) And DMW can also be different.

The above for personal summary, for reference only, if there is infringement please inform.

The following is a reference

MAB (memory address bus) memory address bus MABW (memory address bus width) memory address bus bit width

MDB (Memory data bus) memory data bus MDBW (memory data bus width) memory data bus bit width

The width (width) of the two above is equal in Von-neumann architecture, i.e. MABW=MDBW.

At a certain bus frequency, the wider the width and the wider the bandwidth, the higher the rate of data access.

Report:

Basic knowledge of the bus:

1. Bandwidth of bus (bus data rate)

The bandwidth of the bus refers to the amount of data transmitted on the bus per unit of time, that is, the maximum steady-state data transfer rate of MB for each banknote clock. The two factors that are closely related to the bus are the bit width of the bus and the frequency of the bus, the relationship between them:

Bus bandwidth = operating frequency of the bus * The bit width of the bus/8 2, the bit width of the bus's bit width refers to the number of bits of the binary data that the bus can transmit at the same time, or the number of bits of the bus, that is, the concept of 32-bit, 64-bit, etc.　　The wider the width of the bus, the greater the data rate per second, and the wider the bandwidth of the bus. 3, the bus operating frequency bus operating clock frequency in MHz, the higher the operating frequency, the faster the bus speed, bus bandwidth wider.

The "bit" of a single chip microcomputer