Timer counter Interrupt

Timer/Counter operation is controlled by Tmod and Tcon two registers, Tcon is control register, control start stop and set overflow flag, tmod determine working mode and function. When the counter overflows, it causes the Tcon register to TF0 or TF1 1, and interrupts the request to the CPU.

Tmod Working mode Register

Tmod in the microcontroller reset all cleared, its high four bit set timer 1, low four bit set timer 0; The four-digit meaning is as follows:

Gate: Gate Control bit, the start stop of =0 timer is controlled by Tcon Register only, =1 is controlled by Tcon controller and external interrupt pin level state.

C/T: Timer and Counter mode selection, =1 for counter mode, =0 for timer mode;

M1M0: Working mode selection bit (not understood).

Tcon Control Register

You have the following meanings

TF1: Timer 1 full overflow, TF1 1, start interrupt;

TR1: Timer 1 operation control bit;

IE1: External interrupt 1 request flag;

IT1: External Interrupt 1 Trigger mode Select bit, =0 is level trigger mode, low level is active, =1 is the jump edge trigger mode, from high to low negative jump effective.

Timer counter Interrupt