(turn) Common LCD interface

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Kernel: linux2.6/linux3.0
System: android/android4.0

Platform: Samsung Exynos 4210, Exynos 4412, Exynos 5250

TFT-LCD commonly used interface, TTL (RGB), LVDS, EDP, MIPI, this article we roughly say the signal composition of these interfaces has the basic principle.

First, TTL

1. TTL Interface overview

TTL (transistor transistor logic) is transistor-transistor logic, and TTL level signals are generated by TTL devices. TTL device is a major category of digital integrated circuit, it is manufactured by bipolar process, it has high speed, low power consumption and many kinds of features.

TTL interface is the interface of parallel transmission of data, the use of such an interface, do not need to be in the LCD driver board end and the LCD panel end using a dedicated interface circuit, but by the driver board Master chip output TTL data signal transmitted directly to the LCD panel of the sender interface. Because the TTL interface signal voltage is high, the connection is many, the transmission cable length, therefore, the circuit's anti-jamming ability is inferior, and is prone to produce the electromagnetic interference (EMI). In practical applications, the TTL interface circuit is used to drive small-size (below 15in) or low-resolution LCD panels. The TTL maximum pixel clock is only 28MHz.

TTL is the signal when TFT-LCD only recognizable signal, the early digital processing chips are TTL, that is, RGB direct output to TFT-LCD.

2. Signal type of TTL interface

The driver board TTL output interface generally contains the RGB data signal, clock signal and control signal three kinds of signals. As shown in the following:

(1) RGB data signal

A, single channel TTL

Single-channel 6bit TTL output interface

For 6bit single-channel TTL output interface, a total of 18 RGB data lines, respectively, R0~R5 red primary color data 6, G0~g5 green color data 6, B0~B5 Ottolenghi color data 6, total 3*6=18 bar. Because the base color RGB data is 18bit, it is also called a 18-bit or 18bitTTL interface .

Single-channel 8bit TTL output interface

For 8bit single-way tti, output interface, a total of 24 RGB data lines, respectively, R0~R7 red color data 8, B0~b7 green color data 8, Bo~b7 Ottolenghi color data 8, a total of 3*8=24 bar. Because the base color RGB data is 24bit, it is also called a 24-bit or 24bitTTL interface .

b, dual-channel TTL

Dual channel, that is, two sets of RGB data, divided into odd channel, even channel, the clock is also divided into OCLK/ECLK, Some common one , we painted two, as follows:

Dual-channel 6bit TTL output interface

For 6bit two-way TTL, output interface, a total of 36 RGB data lines, respectively, the odd road RGB data line 18, even the RGB data line 18, 3*6*3=36 Bar. Because the base color of the Rob data is 36bit, it is also called a 36-bit or 36bitTTL interface .

Dual-channel 8bit TTL output interface

For the 8bit dual TTL output interface, a total of 48 RGB data lines, respectively, the odd road RGB data line 24, even the RGB data line 24, 3*8*2=48 Bar. Because the base color RGB data is 48bit, it is also called a 48-bit or 48bitTTL interface .

(2) clock signal

Refers to a pixel clock signal, which is the benchmark for transmitting data and reading data signals. When using the odd/Idol dual way to transmit RGB data, different output interfaces use pixel clocks differently. Some output interface odd/Idol dual data share a pixel clock signal, and some output interface odd/Even two sets of odd pixel data clock and even pixel two clock signal to adapt to the needs of different LCD panels.

(3) Control signal

The control signal includes a data enable signal (or a valid display data selection communication number) DE, line synchronous signal HS, field sync signal vs.

Second, LVDS

1, LVDS Interface overview

The LVDS, or low Voltage differential signaling, is an interface for differential signaling technology. A digital video signal transmission method is developed to overcome the disadvantage of large power consumption and EMI electromagnetic interference when transmitting wideband high bitrate data at TTL level. The LVDS output interface utilizes a very low voltage swing (approx. 350mV) to transmit data via differential transmission on two PCB traces or a pair of balanced cables, i.e. low-voltage differential signal transmission. The LVDS output interface allows the signal to be transmitted at a rate of hundreds of Mbit/s on a differential PCB line or balanced cable, resulting in low noise and low power dissipation due to low-voltage and low-current drive modes.

2, the composition of the LVDS interface circuit
In a liquid crystal display, the LVDS interface circuit consists of two parts, the LVDS output interface circuit (LVDS transmitter) on the motherboard side and the LVDS input interface circuit (LVDS receiver) on the LCD panel side. The LVDS transmitter converts the TTL signal into an LVDS signal and then transmits the signal to the LVDS decoder IC at the LVDS receiver side of the LCD panel via a flexible cable (line) between the drive plate and the LCD panel, and the LVDS receiver then converts the serial signal to a parallel signal of the TTL level. Sent to the LCD screen timing control and row-and-column drive circuit. In fact, the TFT only recognizes TTL (RGB) signals. This part of our approach to Samsung is much more, because Samsung chips do not have LVDS output, so we use the LVDS interface of the TFT-LCD when the need to add a (RGB-LVDS) conversion chip, which we focus on later.

3. Signal type of LVDS interface

The LVDS signal consists of a data differential and a clock differential signal. As shown in the following:

(1), single channel LVDS

Single-channel 6-bit data (if 6-bit y3m/p This set of red lines is not)

There are 4 sets of differential lines, 3 sets of signal lines, and a set of clock lines. y0m, y0p, y1m, y1p, y2m, y2p, Clkout_m, clkout_p.

Single channel 8-bit data

There are 5 sets of differential lines, 4 sets of signal lines, and a set of clock lines. Are y0m, y0p, y1m, y1p, y2m, y2p, Clkout_m, clkout_p, respectively.

(2), dual channel

LVDS in the transmission of high-resolution data, anti-interference ability is stronger, but 1920x1080 above the resolution, a single way overwhelmed, so there are two interfaces appear. The purpose is simple, speed up, enhance anti-jamming ability.

Dual channel 6-bit data

Just twice times the single channel, the clock is also two, the red part: y3m, y3p, Y3M1, y3m1 These two sets of signals are not connected.

Dual Channel 8-bit data

Similar to the previous comparison.

Third, EDP

This interface is unfamiliar, I touch a screen IPAD3, for high-definition screen, such as 2048*1536,goole N10 resolution 2536* is also used this interface.

(in the middle of the arrangement ...)

Four, MIPI interface

This our company has products, but other platforms, not our debugging, I have not contacted. Just a little bit. It feels like this interface is very similar: LVDS, EDP, HDMI, MIPI, are differential information + differential clocks.

(in the middle of the arrangement ...)
Five, TTL (RGB) converted to LVDS

We have used two chips in the project: sn75lvds83b, thc63lvd827 (can output dual LVDS), to sn75lvds83b to illustrate.

1, sn75lvds83b, the main control, LVDS interface LCD relationship

As shown in the SN75LVDS83B application:

is actually: the Samsung chip output TTL (RGB) signal is converted to the LVDS differential signal output of the LCD receiver.

The hardware interface is as follows:

2. sn75lvds83b Reference Circuit

In fact, this part should pay attention to the number of LCD, your screen is 16bit, 18bit, or 24bit, different digits of the LCD has different hardware wiring method. As the AP end mentioned by Samsung EXYNOS4412, the wiring diagram for the different bits output.

(1), 24bitRGB 24bit LCD

Notice the use of five sets of differential signal lines, four sets of signals a set of clocks.

(2), 24bitRGB 18bit LCD

Notice the use of four sets of differential signal lines, three sets of signals a set of clocks, y3m, y3p is NC. AP-Side RGB Wiring method is not the same, 6, 72 bit ground.

If you press thewiring method (24bit output) in (1), connect the 18bit screen. 18bit screen RGB (solid color) signal display is normal, but there is a picture, gradient is not normal. It's been a long time arguing with the hardware, but it's better to solve the problem. To do technical practice is a very important link, some of the misunderstanding of the knowledge, it will lead to work errors.

Six,RGB conversion into EDP

We ordered a screen, but the resolution is too large, our system is very card, and finally stopped.

The circuit diagram is as follows:

：

The EDP signal is similar to that of LVDS, but with a more HPD signal.

Reprinted from xubin341719, thanks to xubin341719 's selfless bong

(turn) Common LCD interface