Volatile and non-cacheable

In some applications, some specific addresses could need to is read from their physical locations each time they is Accesse D (e.g., a status register within FPGA).

The L2 controller offers registers that control whether certain ranges of memory is cacheable, and whether one or more re Questors is actually permitted to access these ranges. The registers is referred to as MARs (memory attribute registers).
note-using the volatile keyword in the C language does not protect a variable from being cached. If an application uses a memory location periodically updated by external hardware, in order to protect the operation in C code Follow these-steps:
Use the volatile keyword to prevent, the code generation tools from incorrectly optimizing the variable.
You must program the MAR register of the range containing the variable to prevent caching.

The role of the volatile keyword in C code, in addition to preventing the CPU from directly using the register and the cache variables, only the global symbols that may be modified in other modules, only when writing concurrent programs, it is possible to use the need for volatile.