Vpfe register description

Vpfe
1. Overview
1.1 CCDC
1) generation of SD and HD time series signals
2) lens shading correction ).
3) supports bt656, ycbcr422 (8bit, 16bit, with HS, VS), and 14bit raw data from CCD/CMOS.
4) programmable 14bit to 8bit output
5) data can be written to DDR through the external write active signal en control
6) The sensor CLK can reach 75 MHz. If H3A is used, it can only reach 67.5 MHz.
7) defect correct
1.2.h3a
1) Auto White Balance and auto eexposure by collecting metrics (Statistics)
2) read and write DDR
3) receive raw data only
1.3.ipipe
1) receives raw data only and converts 14bit raw data to ycbcr422 or ycrcr422 resize.
2) support for RGB Bayer pattern and color space conversion and cmyg
3) Gain Control for each component
4) programmable conversion coefficient of RGB to YCbCr
5) You can set the parameter to only resize mode, that is, directly ycbcr422 resize, which is not processed by other modules.
6) RGB (32bit/16bit) output to SDRAM
7) at least 8 pixel/line and 4 lines of blank are required. In one shot, at least 10 lines of blank are required. After processing
8) supports up to 1344 pixel Input and Output widths.
9) defect correct
1.4.ipipeif
1) read CCDC, SDRAM, and write ipipe
2) re-adjust HD, Vd, and pclk timing to the ipipe input.
3) noise reduction by the black frame Elimination Division of the dark-frame subtract (used for noise points caused by long-time attention light)
2. Pin IO Interface
1. Yin [7 .. 0]/ccdin [7 .. 0]
2. Cin [5 .. 0]/ccdin [13 .. 0]
3. pclk
4. cam_hd, cam_vd
5. cam_wen_field:/set CCD write enable/field ID signal
1) Field Identification signal. fldmode is provided by CCD, csf-idmd, and fldpol.
2) For Wen use, exwen open, wenlog set and or, which is consistent with the valid pixels in the FLAC, nph, SLV, and nlv. And or
Ram mode pins:
All of the above are required
When the other is less than 14bit, CCD [13 .. 0] is generally used for high positions, excluding the base position when SPI is used.
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Pin configuration REG: pinmux0 (vpfe. pdf page38)
3. Vpfe/ISP Integration
Vpss events: 9 are sent as interrupt to arm, and 4 are sent as event to edma
Number acronym module description
0 CCDC vdint0 CCDC triggered after a programmable number of input lines for each frame.
1 CCDC vdint1 CCDC triggered after a programmable number of input lines for each frame.
2 CCDC vdint2 CCDC triggered at the rising edge of Wen Signal
3 h3aint H3A triggered at the end of AF or AEW writes to DDR for each frame
4 vencint Venc triggered at the rising edge of vsync
5 osdint OSD triggered at the end of each frame read from DDR
6 ipipeifint ipipeif triggered at the rising edge of VD if enabled
7 ipipe_int0_hst ipipe triggered when histogram processing is finished for each frame
8 ipipe_int1_sdr ipipe triggered when writes to DDR are finished for each frame
9 ipipe_int2_rza ipipe triggered when the number of lines programmed has been output of rza
10 ipipe_int3_rzb ipipe triggered when the number of lines programmed has been output of rzb
12 ipipe_int5_mmr ipipe triggered when MMR modifications for the next frame can be made
Interrupt: vpssbl. intsel Selection
Int number acronym
0 vpssint0
1 vpssint1
2 vpssint2
3 vpssint3
4 vpssint4
5 vpssint5
6 vpssint6
7 vpssint7
8 vpssint8
Event: vpssbl. evtsel Selection
Event number binary event name
4 0000100 vpssevt1
5 0000101 vpssevt2
6 0000110 vpssevt3
7 0000111 vpssevt4
Vpss REG:
Vpfe module register Map
Vpss registers address range size
Vpssclk 0x01c70000 0x01c7007f 128b
H3A 0x01c70080 0x01c700ff 128b
Ipipeif 0x01c70100 0x01c701ff 256b
OSD 0x01c70200 0x01c702ff 256b
Venc 0x01c70400 0x01c705ff 512b
CCDC 0x01c70600 0x01c707ff 512b
Vpssbl 0x01c70800 0x01c708ff 256b
Ipipe 0x01c71000 0x01c73fff 12 k-
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4. Vpfe/ISP functional description
4.1 CCDC
Parameter: select the data output from modeset. inpmod to DDR, YCbCr or RGB.
RAW mode time series parameters: HDW, vdw, PPLN, hlpfr (from AFE)
In RAW mode, ccdcfg. ycinswp = 0
4.1.2.1 digital clamp
The Black Level of the clamp can be calculated from the pixel or from the black side of the CCD sensor, and the base amount can be extracted from the left black side.
To calculate the average value.
Parameter: Clamp. obst black pixel start point; clamp. obslen is used to calculate the average number of rows in each row; dcsub. obsln is used to calculate the average number of rows.
4.1.2.2 color space conversion
Cscctl [0] enabled. Composed of a multiplier and line memory, cmyg -- "rgbg
Specifies the data area for fmt7d, fmtlnh, fmtslv, and fmtlnv.
After conversion, the data will have a row of latency (latency ).
The last row must have at least one invalid pixel and at least one invalid row in a frame.
4.1.2.3 defect correction: Bad point correction
Dfcctl [0] enabled, 1024 points can be corrected
4.1.2.4 lens shading correction: Lens shadow correction
Lsccfg [0] is enabled. The center of the lens fades to the edge. Thus correction
4.1.2.5 black level compensation: too bright, too dark Compensation
Blkcmp0.r _ ye, blkcmp0.gr _ cy, blkcmp1.gb _ g, blkcmp1. B _ Mg)
4.1.2.6 median filter: central filter. Send SDRAM one way, and ipipe one way.
1. Average filter configuration
2. Median Filter Configuration
Gammawd. mfilt1 and gammawd. mfilt2
4.1.2.7 SDRAM raw output formatting
4.1.4 data output control
• Sdofst. fiinv-invert interpretation of the field ID signal
• Sdofst. fiinv-invert interpretation of the field ID signal
• Sdofst. lofts0-offset, in lines, between even lines on even fields (field 0)
• Sdofst. lofts1-offset, in lines, between odd lines on even fields (field 0)
• Sdofst. lofts2-offset, in lines, between even lines on odd fields (Field 1)
• Sdofst. lofts3-offset, in lines, between odd lines on odd fields (Field 1)
4.2 ipipeif
Parameters: HDW = 8 pixel, vdw = 4 Line (CONTINUE) or 10 line (one shot), PPLN = HD interval, LPFr = VD interval> 1 line, hnum = horizontal valid pixels (starting from the rising edge of HD ???), Vnum = vertical valid pixel (starting from VD descent edge, that is, every 4 or 10 lines)
4.2.1.1 CCDC raw input mode (CFG. inpsrc = 0)
14bit
4.2.1.2 SDRAM raw input mode (CFG. inpsrc = 1 h)
Read 8-bit or 16-bit from SDRAM, 8-bit is compressed by the A-LAW, you can set cfg. ialaw decompression, you can also fill in 0 to complete
4.2.1.3 CCDC raw input with dark frame subtract from SDRAM mode (CFG. inpsrc = 2 h)
Ipipeif input = CCDC raw input-SDRAM Input
In this case, the meaning of PPLN and LPFr is different from that of other input modes, indicating the starting position of the horizontal and vertical direction when the data is subtracted from the CCDC data.
4.2.1.4 SDRAM YCbCr 4: 2 input mode (CFG. inpsrc = 3 H)
16bit YCbCr data
4.2.2 timing generation
When the input is 0 or 2, Hd/VD/Wen and pclk are provided by CCDC. If the input is 1 or 3, ipieif generates Hd/VD (based on LPFr and PPLN ), pclk can continue to use pclk (CFG. clksel = 0), can also be generated by yourself (CFG. clksel = 1) (vpssclk-based cfg. clkdiv). When pclk is generated, you must consider the maximum clock requirements and real-time SDRAM operation requirements for ipipe resize below.
When cfg. inpsrc is not 0, ipipe I/F SDRAM data can be read in a timely order in one-shot or in continue mode (Enable. Enable)
When the input is greater than 1344pixel, open cfg. decm to set the proportional coefficient to reduce to less than 1344.
4.3 ipipe
Parameter: ipipe_hst, ipipe_vst defines the start point (with the rising edge of HD and VD as the origin point), ipipe_hsz, ipipe_vsz defines the size of the data area to be processed
Ipipe_colpat defines the color pattern for processing data
Input modes (ipipe_dpaths.fmt)
0: raw to YCbCr
1: raw to raw
2: raw to boxcar
3: YCbCr to YCbCr
In raw pass through mode, which can support a maximum of 4096 pixel/line and be directly written to SDRAM
4.3.3 defect correction
4.3.4 Noise Filter
4.3.5 pre Filter
To reduce line-crawling, there are only two methods for green pixels. (pre_typ option): 1. Constant 2. Algorithm
4.3.6 White Balance
White Balance is to adjust the gain. There are two types:
1. Adjust the total brightness of the digital gain image, x 0-x 3.996 (step = 1/256)
2. White Balance gains adjusts the gain of each component in CFA, x 0-x 7.992 (step = 1/128)
4.3.7 CFA Interpolation
Converted from Bayer RGB to RGB data
4.3.8 rgb2rgb Blending (hybrid)
RGB mixture, that is, an offset is added to tune the human color spectrum. (Rgb_mul _ [R, G, B] [R, G, B], & rgb_oft _ [R, G, B])
4.3.9 Gamma Correction Module
The relationship between brightness and voltage during video recording is called the gamma curve, and Gamma Correction is used to correct the non-linearity.
There are three channels: 1. Bypass 2. From RAM Table 3. From Rom table
4.3.10 rgb2ycbcr conversion module
Ycc_mul _ [R, G, B] [y, CB, Cr], and ycc_oft _ [y, CB, Cr]
4.3.11 conversion module
Convert to ycbcr422 format
4.3.12 2-D edge Enhancer
Improves Image Quality Based on Brightness signals. Enable yee_en.en. Use a Qualcomm filer to obtain the image edge. The filer coefficient is programmable (yee_mul _ [, 2] [, 2]), and the output can be down SHIFT (yee_shf.shf ). Added Ram table values to enhance sharpness.
4.3.13 median NR
Used to reduce the pseudo peak (false peak) of edge strength, yee_emf.en Enabled
4.3.14 chrominance Suppression
Enable fcs_en.en. In areas with high brightness, there may be one or two color channels saturated, but other colors do not, which will lead to false colors, for example, the most common appearance is that the original is white but the appearance is pink, the color suppression can reduce false color.
4.3.15 horizontal and vertical resize Module
Range: x1/16 scale-down to X8
Parameter: rsz [N]. rsz_h_typ type selection, hrsz (rsz [N]. rsz_h_dif) and vrsz (rsz [N]. rsz_v_dif) ratio, the upper and lower limits of 32-4096, corresponding to the X8-X1/16, the actual 256/hrsz, 256/vrsz, the maximum image output size is 1344 pixels/line for rsz [0] and 640 pixels/line for rsz [1].
Vertical resize has two modes: Input row number mode (rsz_seq.tmm = 1) and continuous mode. Rsz [N]. rsz_v_phs_o defines the final output position
4.3.16 output interface
Ycc_y_max, ycc_y_min, ycc_c_max, and ycc_c_min define the size range of Y and C, ycbcr422 to ycbcr444, to RGB, and output 32bit
4.3.17 RGB Converter
In H/V resizer, ycbcr422 is converted to ycbcr444 through linear interpolation. Due to this relationship, two pixels before and after the first row will be lost, that is, after resize, two pixels are less than expected.
Access the data in the data packaging mode in the SDRAM burst (256bit). There are two packaging methods: 32bit, 16bit, (rsz [N]. rgb_typ.typ. 8 bits of RGB and 8 bits of Alpha value (in rsz [N]. rgb_bld setting); in 16-Bit mode, R (5-bit), g (6-bit), and B (5-bit) are input to SDRAM.
4.4 H3A
5 Programming Model
Vpfe memory master Selection
Shared Memory register field settings
Shared read buffer (sulfate) PCR. rblctrl 0: ipipeif
1: Reserved
2: H3A
Shared write buffer (SWB) PCR. wblctrl 0: ipipeif
1: Reserved
DFC table memctrl. dfcctrl 0: ipipe
1: CCDC
Rsz line memory memctrl. rsz_ctrl 0: ipipeif
1: Reserved
5.4 programming CCDC
Module active: syncen. vdhden active CCDC, you need to set some Reg before active.
Syncen. Wen write SDRAM active
If CCDC is in master mode, data is processed immediately after syncen. vdhden.
If CCDC is slave mode, syncen. vdhden should be enabled before external devices to avoid data loss.
Set order:
1. Set Data Output address (stadrh & stadrl ).
2. Enable Hd/VD and Wen at the same time (modeset. Wen & syncen. vdhden)
Interruption:
Vdint0, vdint1, and vdint2
Vdint0 and vdint1 are interrupted when they reach the number of rows in vdint. vdint0 and vdint. vdint1
Vdint2 uses cam_wen_field as a reference and interrupts along the descent edge.
Modeset. fldstat field status indication
Reg can be divided into two types:
Shadowed registers (event latched registers)-it can be read and written at any time, but it only works when certain events occur.
Busy-writeable registers
5.5 programming the image pipe interface (ipipeif)
Module active: Enable. Enable. When the input is CCDC raw, it does not need to be active.
When the input is SDRAM, CFG. oneshot defines the oneshot mode or the continous mode. In oneshot mode, only one frame is processed, and enable. Enable automatically clears 0.
An ipipeif event to the vpssbl is generated.
5.6 programming the image pipe (ipipe)
Module active: ipipe_en.en
Ipipe event
Irq0 final pixel from each frame is flushed from the image pipe (not resizer) and histogram completion event
Irq1 SDRAM write completion event
Irq2 rza interval completion event
Irq3 rzb interval completion event
Irq5 register Update ready notification event
5.6.1.2.1 resizer Bypass Mode
Since the YCbCr data still passes through the rza block in resizer bypass mode, the following registers
Must be set accordingly:
Gck_sdr = 0 rsz [0]. rsz_v_dif = 256
Rsz_seq.seq = 0 rsz [0]. rsz_h_phs = 0
Rsz_seq.tmm = 0 rsz [0]. rsz_h_dif = 256
Rsz_aal = 0 rsz [0]. rsz_h_lse = 0
Rsz [0]. rsz_o_hps = 0 rsz [1]. rsz_en = 0
Rsz [0]. rsz_v_phs = 0
5.6.1.2.2 raw input, raw output mode (ipipe_dpaths.fmt = 1)
In this mode, the raw data bypasses the raw to YCbCr processes (see Figure 37), but since it still
Passes through The YCbCr processing blocks, the following registers must be set accordingly:
Ipipe_dpaths.fmt = 1 yee_en = 0 rsz [0]. rsz_v_dif = 256
Box_en = 0 fcs_en = 0 rsz [0]. rsz_h_phs = 0
Ycc_adj.ctr = 16 rsz_seq.tmm = 0 rsz [0]. rsz_h_dif = 256
Ycc_adj.brt = 0 rsz [0]. rsz_en = 1 rsz [0]. rsz_h_typ = 0
Ycc_y_min = 0 rsz [0]. rsz_ I _vps = 0 rsz [0]. rsz_h_lse = 0
Ycc_y_max = 255 rsz [0]. rsz_ I _hps = 0 rsz [0]. rsz_h_lpf = 0
Ycc_c_min = 0 rsz [0]. rsz_o_hps = 0 rsz [0]. rsz_rgb_en = 0
Ycc_c_max = 255 rsz [0]. rsz_v_phs = 0 rsz [1]. rsz_en = 0
5.6.1.3.1 read/write procedures
The ipipe internal memory values can be written, read, and written after read. If multiple values need
Be set in incremental addresses, then the ram_mode.adr bit can be set so that only the first address
Needs to be set and subsequent reads/writes will auto-increment the internal address. The following
Procedures shoshould be followed to access the internal memories:
For memory write:
1. Write to ram_mode: Set memory selection and set ext = 0 andwdt = 1.
2. Write to ram_adr: Set starting offset into memory.
3. Write to ram_wdt: write data.
For memory read:
1. Write to ram_mode: Set memory selection and set ext = 0 andwdt = 0.
2. Write to ram_adr: Set starting offset into memory.
3. Write to ram_wdt: Write dummy data.
4. Read the data of the internal memory from ram_rdt.
For memory write after Read:
1. Write to ram_mode: Set memory selection and set ext = 0 andwdt = 1.
2. Write to ram_adr: Set starting offset into memory.
3. Write to ram_wdt: write data.
4. Read the data of the internal memory from ram_rdt.
5.7 programming the hardware 3A (H3A)
Module activity: PCR. af_en, PCR. aew_en
When the input is SDRAM, the one-shot mode is used. to process each frame, set PCR. sdr_fetch_en.
When the input is CCDC, it is processed in the continuous mode. In this case, it is processed according to the CCDC sequence.
After processing a frame, this module can generate a single break and an event.
5.8 programming the buffer logic (vpssbl and vpssclk registers)
Vpssbl and vpssclk required configuration parameters
Function configuration required
CCDC vpssbl. memctrl. dfcctrl
Vpssclk. clkctrl. ccdcclk
Ipipeif vpssbl. PCR. rblctrl
Vpssclk. clkctrl. ipipeclk
Ipipe vpssbl. PCR. wblctrl
Vpssbl. memctrl. ipipe_wd_en
Vpssbl. memctrl. resz_ctrl
Vpssbl. memctrl. dfcctrl
Vpssclk. clkctrl. ipipeclk
H3A vpssbl. PCR. rblctrl
Vpssclk. clkctrl. h3aclk
Vpssbl. intsel and vpssbl. evtsel are selected for interruptions and events.