Why is the x86cpu real-mode protection mode unclear? Cr0 register based on Xv6-OS Analysis

Cr0 register based on Xv6-OS Analysis

I always felt dizzy before... What? When to switch the real model, how to switch, and why?

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The following code is from the boot/boot. s file of xv6.

This is the "watershed" of the CPU real model and protected model"

The root cause is the changes in the Cr0 registers that control the two running modes.

In xv6, this kind of CPU mode switching occurs very early. After several Assembly commands of boot. s are executed, the switch is immediately executed. After the switch, the CPU runs with the protected model.

The following is layout of Cr0.

Check the code again (cr0_pe_on is defined at the beginning of boot. s and the value is 1)

The minimum position of the Cr0 register is 1, so... pe goes through this process and enters the protected model.

PE: Protection enable is enabled for 0 bits of Cr0 ). When this bit is set, the protection mode is enabled. When the system is powered on and reset, this bit defaults to 0, so it is the real model. when PE is set to 1, segment-level protection is enabled, that is, only segment protection is performed, and the paging mechanism is not enabled. If you want to enable the paging mechanism, you need to set both PE and PG

As a matter of fact, you can find out when the protection mode will be enabled and how to enable it.

Next, let's continue to see what "baby" exists in Cr0"

PG: The paging flag. When this bit is set, the paging mechanism is enabled. When the bit is reset, the paging mechanism is disabled. At this time, all linear addresses are equal to physical addresses. You must enable or disable PE before enabling this flag. If you enable pagination, Pe Pg is set to 1 at the same time.

WP :( intel 80486 or more machines will have) this bit is the write protection bit, write protection bit. when this bit is 1, the CPU will prohibit the user from writing data to read only page at the privileged level of 0 (Super User. However, it is allowed to be reset. This flag is mainly related to cow (copy on write.

Ne: Number error coprocessor error. When the value is 1, The x87 coprocessor internal reporting mechanism is enabled. If the value is 0, the x87 coprocessor report mechanism in PC form is used. (I don't feel like I am going to touch this stuff at the moment ..)

Be careful when changing Pe Pg. Only when the execution program has at least some code and data with the same address in the linear address space and physical address space can we change the PG bit settings. In this case, code with the same address serves as a bridge between paging and pagination. Whether or not the paging mechanism is enabled, the Code has the same address. In addition, you must refresh TLB before enabling paging Pg = 1. After PG is modified, you must use a long jump statement to refresh any commands in different modes that have been obtained in the processor execution pipeline.

Et: The system has 80387 coprocessor, set to 1, there is a 80287 or no, set to 0

TS em MP is related to floating point processing.

Why is the x86cpu real-mode protection mode unclear? Cr0 register based on Xv6-OS Analysis