Write Makefile with Me (Iv.)

Writing rules
————

The rule contains two parts, one is a dependency, and one is the method of generating the target.

In Makefile, the order of the rules is important because there should be only one final goal in Makefile, and all other goals are associated with this goal, so make sure you know what your ultimate goal is. In general, there may be a lot of goals defined in makefile, but the goals in the first rule will be established as the ultimate goal. If there are many goals in the first rule, then the first goal will be the ultimate goal. Make is the goal that is accomplished.

Well, let's take a look at how to write the rules.

I. Examples of rules

FOO.O:FOO.C defs.h # foo Module
Cc-c-G foo.c

See this example, you should not be very unfamiliar, as has been said before, FOO.O is our goal, FOO.C and Defs.h is the target of the source file, and only one command "cc-c-G foo.c" (beginning with the TAB key). This rule tells us two things:

1, file dependencies, foo.o rely on foo.c and defs.h files, if foo.c and defs.h file date than foo.o file date to new, or FOO.O does not exist, then dependency occurs.
2. If you generate (or update) FOO.O files. That's the CC command, which explains how to generate the foo.o file. (Of course foo.c files include defs.h files)

Ii. The grammar of the Rules

Targets:prerequisites
Command
...

or so:

Targets:prerequisites; Command
Command
...

Targets is the filename, separated by a space, and you can use wildcard characters. In general, our goal is basically a file, but it can also be multiple files.

command is the command-line, and if it is not on a line with "target:prerequisites," you must start with [tab], and if you are on a line with prerequisites, you can separate it with a semicolon. (see above)

Prerequisites is the file (or target) on which the target depends. If one of these files is newer than the target file, the target is considered "obsolete" and is considered to be rebuilt. That's already been said before.

If the command is too long, you can use the backslash ('/') as the newline character. Make has no restrictions on how many characters are on a line. Rules tell make two things, file dependencies, and how to become target files.

In general, make executes commands in the standard shell of Unix, which is/bin/sh.

use wildcard characters in rules

If we want to define a series of similar files, it is natural for us to think of using wildcard characters. Make supports three wildcard characters: "*", "?" and "[...]". This is the same as the B-shell of UNIX.

The tilde ("~") character also has a special purpose in the file name. If it is "~/test", this represents the test directory under the current user's $home directory. "~hchen/test" indicates the test directory under the user Hchen host directory. (These are all small knowledge under UNIX, make is supported) and in Windows or MS-DOS, the user does not have a host directory, then the directory of the wave number depends on the environment variable "home".

Wildcards replace your series of files, such as "*.c", which indicates a later suffix of c. One need to note that if we have wildcard characters in the filename, such as "*", then you can use the escape character "/", such as "/*" to represent the true "*" character, rather than any length of string.

Well, let's take a look at some examples first:

Clean
Rm-f *.O

The above example I do not say more, this is the operating system shell supported wildcard characters. This is the wildcard character in the command.

Print: *.C
Lpr-p $?
Touch Print

The above example shows that wildcards can also be in our rules, target print depends on all of the [. c] files. Where the "$?" is an automation variable that I will tell you later.

objects = *.O

The above example shows that a wildcard can also be used in a variable. Not that [*.O] will unfold, no. The value of objects is "*.O". The variables in makefile are actually macros in C/s + +. If you want the wildcard character to expand in a variable, that is, let the value of objects be a collection of file names for all [. O], then you can:

Objects: = $ (wildcard *.o)

This usage is indicated by the keyword "wildcard", which we will discuss later on in the Makefile keyword.

Iv. Document Search

In some large projects, there are a large number of source files, and our usual practice is to classify the many source files and store them in different directories. So, when make needs to look for file dependencies, you can add a path to the file, but the best thing to do is to tell make on a path that makes it look for it automatically.

The special variable "VPATH" in the makefile file completes this function, and if you do not specify the variable, make will only look for dependent and target files in the current directory. If you define this variable, make makes a search for the file in the specified directory when the current directory is not found.

VPATH = src:.. /headers

The definition above specifies two directories, "src" and "... /headers, make the search in this order. The directory is delimited by "colon". (Of course, the current directory is always the highest priority search place)

Another way to set a file search path is to use make's "vpath" keyword (note, it's all lowercase), which is not a variable, it's a make keyword, which is similar to the Vpath variable mentioned above, but it's more flexible. It can specify different files in a different search directory. This is a very flexible feature. There are three ways to use it:

1, Vpath <pattern> <directories>

Specify search directory <directories> for files that conform to mode <pattern>.

2, Vpath <pattern>

Clears the search directory for files that conform to mode <pattern>.

3, Vpath

Clears all file search directories that have been set up.

The <pattern> in the Vapth use method needs to include the "%" character. "%" means to match 0 or more characters, for example, "%.h" means all files ending with ". h". <pattern> Specifies the set of files to search for, while <directories> specifies the directory of the search for the <pattern> set of files. For example:

Vpath%.h. /headers

This statement indicates that make is required in the. /headers directory to search for all files ending with ". h". (If a file is not found in the current directory)

We can use the Vpath statement continuously to specify different search strategies. If the same <pattern> is present in a continuous vpath statement, or if the <pattern> is repeated, then the search is performed in the order of the Vpath statement. Such as:

Vpath%.c foo
Vpath% Blish
Vpath%.c Bar

The file that ends with ". C" is first in the "foo" directory, then "Blish", and finally the "bar" directory.

Vpath%.c Foo:bar
Vpath% Blish

The above statement represents the end of the ". C" file, first in the "foo" directory, then the "bar" directory, and finally the "Blish" directory.

v. Pseudo-Target

In one of the earlier examples, we mentioned a "clean" goal, which is a "pseudo target",

Clean
RM *.O Temp

As in the case of "clean" in our previous example, we generate a lot of file-compilation files, and we should also provide a "target" to clear them for full recompilation. (Use this target as "make clean")

Because, we do not generate "clean" this file. "Pseudo-target" is not a file, just a label, because "pseudo target" is not a file, so make cannot generate its dependencies and determine whether it is to be executed. We can only make it effective by indicating this "goal" by showing it. Of course, the "pseudo target" name can not be the same as the file name, otherwise it lost the meaning of "false target".

Of course, in order to avoid this situation with duplicate files, we can use a special tag. Phony "to show that a target is a" pseudo target "and to make that, whether or not there is a file, the goal is" pseudo target. "

. Phony:clean

As long as there is a statement, whether or not there is a "clean" file, the goal of "clean" is to run. So the whole process can be written like this:

. Phony:clean
Clean
RM *.O Temp

Pseudo-targets are generally not dependent on files. However, we can also specify which files are dependent on the pseudo target. Pseudo targets can also be "default targets" as long as they are placed first. An example would be if your makefile needs to generate several executables in one breath, but you just want to simply knock a make, and all the target files are written in a makefile, then you can use the "pseudo target" feature:

All:prog1 prog2 Prog3
. Phony:all

PROG1:PROG1.O UTILS.O
Cc-o Prog1 PROG1.O UTILS.O

prog2:prog2.o
Cc-o prog2 PROG2.O

PROG3:PROG3.O SORT.O UTILS.O
Cc-o prog3 prog3.o SORT.O UTILS.O

We know that the first goal in Makefile will be used as its default target. We have declared a false goal of "all", which relies on three other targets. Since the nature of the pseudo target is always performed, the three goals it relies on are always less than the "all" target. Therefore, the rules of the other three goals will always be resolved. It has reached our goal of generating multiple goals in one breath. “. Phony:all declared "All" as the target of "pseudo target".

As we can see from the above examples, goals can also be relied upon. Therefore, pseudo targets can also be relied upon. Look at the following example:

. Phony:cleanall Cleanobj Cleandiff

Cleanall:cleanobj Cleandiff
RM Program

Cleanobj:
RM *.O

Cleandiff:
RM *.diff

Make clean clears all files that will be purged. The two pseudo goals of "cleanobj" and "Cleandiff" are somewhat like the meaning of "subroutine". We can enter the "Make Cleanall" and "Make Cleanobj" and "makes Cleandiff" commands to clear different kinds of files.

Original: http://blog.csdn.net/haoel/article/details/2889