Analysis of uart log that android cannot boot

Source: Internet
Author: User

Analysis of uart log that android cannot boot
Similar to complex R/W mem test fail, it fails in the preloader stage. Please contact the Fraud Department;
[SD0] dat crc error, patch: ALPS00787669;
NAND project:
Init: command r =-1 'mount ubifs ubi @ system/system wait'
Init: command r =-1 'mount ubifs ubi @ userdata/data nosuid nodev wait'
Init: command r =-1 'mount ubifs ubi @ cache/cache nosuid nodev wait'
EMMC project:
Init: command r =-1 'mount ext4/emmc @ android/system noatime ro remount wait'
Init: command r =-1 'mount ext4/emmc @ usrdata/data noatime nosuid nodev wait noauto_da_alloc, discard'
Init: command r =-1 'mount ext4/emmc @ cache/cache noatime nosuid nodev wait noauto_da_alloc, discard'
If any error similar to the NAND project or eMMC project occurs, follow [FAQ05169] [Storage] to return the image from any shard of readback on the mobile phone.
The partition data corresponding to read back. For NAND projects, the page only and page + spare methods are required.
If the Exception stack appears in the log, provide the corresponding symbols version (which must be compiled and generated in the same way as the version in the machine where the log is crawled): \ kernel \ out \ vmlinux
Other Instructions:


[SD0] SET_CLK (52000 kHz): SCLK (50000 kHz) indicates that eMMC works at 52 mhz in the preloader stage.
Msdc0-> !!! Set <200000 KHz> Source <200000 KHz> indicates that eMMC operates at 200 MHZ in the kernel stage.
In the case of data crc error and time out in the log, the eMMC frequency is often reduced. The clk In the pl, lk, and kernel phases is set
\ Mediatek \ platform \ mt6 ××× \ preloader \ src \ drivers \ msdc. c
Void msdc_config_clock (struct mmc_host * host, int ddr, u32 hz)
\ Mediatek \ platform \ mt6 ××× \ lk \ msdc. c
Void msdc_config_clock (struct mmc_host * host, int ddr, u32 hz)
\ Mediatek \ platform \ mt6 ××× \ kernel \ drivers \ mmc-host \ sd. c
Static void msdc_set_mclk (struct msdc_host * host, int ddr, u32 hz)
The corresponding frequency reduction processing modification point removes MSDC_UHS1 from the following three files. You can view the patch: ALPS00787669 for further understanding:


\ Mediatek \ custom \ project \ lk \ cust_msdc.c


\ Mediatek \ custom \ project \ preloader \ msdc_cust.c


\ Mediatek \ custom \ project \ kernel \ core \ src \ board. c

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