How to write the Linux GCC make file-Summary

The directory structure is:

INC/Hello. h

Src/Hello. c

Main/Main. c

Makefile

File Content:

Hello. h:

Void Hello (char name []); <br/>

Hello. C:

# Include <stdio. h> </P> <p> void Hello (char name []) <br/> {<br/> printf ("Hello % s! /N ", name); <br/>}< br/>

Main. C:

# Include <stdio. h> <br/> # include "hello. H "<br/> // The second hello. h shoshould in "" <br/> int main () <br/> {<br/> Hello ("GCC"); <br/> printf ("Haha Linux Ubuntu! /N "); <br/> return 0; <br/>}< br/>

Makefile:

# String declaration <br/> objects = Main. O hello. O </P> <p> # command <br/> app: $ (objects) <br/> CC-O app $ (objects) <br/> main. o: Main. c hello. h stdio. h <br/> CC-C $ <-I. /INC <br/> hello. o: Hello. c stdio. h <br/> CC-C $ </P> <p> # search paths <br/> vpath %. h/usr/include: Inc <br/> vpath %. C main: SRC </P> <p> # clean the intermediate files <br/>. phony: Clean <br/> clean: <br/> RM app *~ $ (Objects) <br/>

First, you need to make it clear that there areTwo execution programs, one make and one GCCIn makefile, the two statements also occupy one line.

The main problem here is the path problem. Because different files are under different directories, we need to tell the path of the program file, and there are two programs that need to be notified.The Methods notified by the two programs are different.This problem has plagued me for a long time. With the help of many people, I have finally understood it.

Make's search path is set to vpath or vpath, which is described in many documents and can be set in all files ,. C ,. H and others.

The GCC search path is set as (this should be the only search path for header files, because it is include):-I Inc,

The search path of the. c file does not seem to be configurable, but can only be written as shown in CC-C path/%. C. This is my understanding.

One way is to write data out of display, and not to use it. %. C also writes data out, that is, makeAutomated Variables.

"$ <" And "$ @" are automation variables. "$ <" indicates all dependent target sets (%. c), "$ @" indicates the target set (%. o ).

(It is the make variable. If the file is not found in the current directory, it will automatically search for the path set in vpath. If this is not used, if. C is not in the current directory.-C should be followed by C to specify the directory location. After using this, you can specify it in vpath)

Because it is a make variable, the make path set with vpath takes effect here, and you do not need to specify the. c path. It is more concise to write in this way.

 

I recently read the code downloaded from the "deep understanding of computer systems" on Linux. I have to write makefile myself, I finally understood a little ~~~

The downloaded code can be easily compiled using this MAKEFILE file:

# String declaration <br/> Path = netp <br/> APP = echoclient <br/> objects = $ (APP ). O csapp. O </P> <p> # command <br/> $ (APP): $ (objects) <br/> CC-o $ (APP) $ (objects) <br/> $ (APP ). o: $ (APP ). c csapp. h <br/> CC-C $ <-I include <br/> csapp. o: csapp. c csapp. h <br/> CC-C $ <-I include </P> <p> # search paths <br/> vpath %. h/usr/include: Include <br/> vpath %. c SRC: $ (PATH) </P> <p> # clean the intermediate files < Br/>. Phony: Clean <br/> clean: <br/> RM $ (APP )*~ $ (Objects) <br/>

You only need to modify the path and app string.