Linux Task Switching code (switch_to)

Copyright 2009 (c) benzus

The following code comes from the Linux-1.0 kernel include/Linux/sched. h file.

(Note that the Linux 0.11 kernel is basically the same as this code, so this article also applies to the 0.11 kernel)

01 # define switch_to (n ){/
02 struct (long a, B;} _ TMP ;/
03 _ ASM _ ("CMPL % ECx, current/n/t "/
04 "Je 1f/n/t "/
05 "xchgl % ECx, current/n/t "/
06 "movw % dx, % 1/N/t "/
07 "ljmp * % 0/n/t "/
08 "CMPL % ECx, % 2/n/t "/
09 "JNE 1f/n/t "/
10 "clts/N "/
11 "1 :"/
12: "M" (* & __ TMP. A), "M" (* & __ TMP. B ),/
13 "M" (last_task_used_math), "D" _ TSS (N), "C" (long) task [N]);/
14}

Note: This is an embedded assembly macro. It switches from the current task to task N and is called in the process scheduler. Next I will comment on it line by line.

Row 2nd defines a structure that contains two long integers.

Row 3rd compares task [N] with current, where task [N] is the task to be switched to, and current is the current task;

Line 2 shows that if the task to be switched to is the current task, the task jumps to the number 1, that is, the end, and does nothing. Otherwise, the following code is executed.

The value of two operands is exchanged in row 5th, which is equivalent to the C code's: Current = task [N], ECx = the task to be switched out (the original task );

The TSS selector of the new task is assigned to _ TMP. B;

Row 7th is the key to understanding the task switching mechanism. Long Jump to * & TMP, causing task switching. The at&t syntax ljmp is equivalent to the intel syntax's JMP far section: Offset, where the (IP) <-_ TMP. a, (CS) <-_ TMP. b. Before its absolute address, add the star number ("*"). When the selection operator of the pointer contained in the Inter-segment command JMP instructs the TSS descriptor of an available task status segment, task switching will occur. So how does the CPU recognize that the descriptor is a TSS descriptor rather than other descriptors? This is because all Descriptors (a descriptor is 64-bit) have four bits to indicate the type of the descriptor. If the descriptor type value is 9 or 11, it indicates that the descriptor is a TSS descriptor. After the CPU obtains the TSS descriptor, it loads it into the task register TR, and then according to the TSS descriptor information (mainly the base address) find the TSS content of the task (including all register information, such as EIP) and start running the new task according to its content. For now, we call this process of restoring all registers to the Register field.

8th ~ The 10 rows determine whether the original task used the coprocessor last time. If yes, clear the TS mark of the Cr0 register.

The 2nd difficulty is that after the execution of line 1, the task is switched (that is, the task is switched to the new task). After the task is switched back, the execution of Line 2 will continue! The following describes the causes.

Since the CPU will recover the register field when the task is switched, it will also save the register field. These registers will be written to the TSS structure of the original task. It is worth noting that the EIP will point to the next instruction (7th rows) that causes the task switching command (8th rows). Therefore, obviously, when the original task is scheduled to run again one day, it will start to run from the place indicated by the EIP (row 8th.